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74LVCH16646APAG

产品描述Bus Transceivers 16-bit Bus Transceiver
产品类别逻辑    逻辑   
文件大小259KB,共8页
制造商IDT (Integrated Device Technology)
标准
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74LVCH16646APAG概述

Bus Transceivers 16-bit Bus Transceiver

74LVCH16646APAG规格参数

参数名称属性值
Brand NameIntegrated Device Technology
是否无铅不含铅
是否Rohs认证符合
厂商名称IDT (Integrated Device Technology)
零件包装代码TSSOP
包装说明TSSOP, TSSOP56,.3,20
针数56
制造商包装代码PAG56
Reach Compliance Codecompliant
ECCN代码EAR99
控制类型INDEPENDENT CONTROL
计数方向BIDIRECTIONAL
系列LVC/LCX/Z
JESD-30 代码R-PDSO-G56
JESD-609代码e3
长度14 mm
逻辑集成电路类型REGISTERED BUS TRANSCEIVER
最大I(ol)0.024 A
湿度敏感等级1
位数8
功能数量2
端口数量2
端子数量56
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP56,.3,20
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)260
电源3.3 V
Prop。Delay @ Nom-Sup5.7 ns
传播延迟(tpd)7.9 ns
认证状态Not Qualified
座面最大高度1.1 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2.7 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Matte Tin (Sn) - annealed
端子形式GULL WING
端子节距0.5 mm
端子位置DUAL
处于峰值回流温度下的最长时间30
翻译N/A
触发器类型POSITIVE EDGE
宽度6.1 mm

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IDT74LVCH16646A
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH16646A
3.3V CMOS 16-BIT BUS
NOT RECOMMENDED
TRANSCEIVER/REGISTER
FOR NEW DESIGNS
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O AND BUS-HOLD
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4μ W typ. static)
μ
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in TSSOP package
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
APPLICATIONS:
• High Output Drivers: ±24mA
• Reduced system switching noise
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
The LVCH16646A 16-bit bus transceiver and register is built using
advanced dual metal CMOS technology. This high-speed, low power
device is organized as two independent 8-bit D-type transceivers with 3-
state D-type registers.The controls circuitry is organized for multiplexed
transmission of data between A bus and B bus either directly or from the
internal storage registers. Each 8-bit transceiver/register features direction
control (DIR), over-riding Output Enable control (OE) and Select lines (SAB
and SBA) to select either real- time data or stored data. Separate clock inputs
are provided for A and B port registers. Data on the A or B data bus, or both,
can be stored in the internal registers by the low-to-high transitions at the
appropriate clock pins. Flow-through organization of signal pins simplifies
layout. All inputs are designed with hysteresis for improved noise margin.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVCH16646A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16646A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
56
29
1OE
1
DIR
1
55
54
2
3
2
OE
28
30
31
27
26
2
DIR
2
CLKBA
2
SBA
2
CLKAB
2
SAB
1
CLKBA
1
SBA
1
CLKAB
1
SAB
1D
One of Eight Channels
1D
One of Eight Channels
C1
52
C1
42
1
A
1
5
1
B
1 2
A
1
15
2
B
1
1D
C1
1D
C1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
JANUARY 2016
DSC-3787/5
© 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

 
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