DATASHEET
CLOCK DIVIDER
Description
The ICS542 is cost effective way to produce a high-quality
clock output divided from a clock input. The chip accepts a
clock input up to 156 MHz at 3.3 V and produces a divide by
2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs
on the chip, one being a low-skew divide by two of the other.
For instance, if an 100 MHz input clock is used, the ICS542
can produce low-skew 50 MHz and 25 MHz clocks, or low
skew 25 MHz and 12.5 MHz clocks. The chip has an
all-chip power-down mode that stops the outputs low, and
an OE pin that tri-states the outputs.
See the ICS541 and ICS543 for other clock dividers, and
the ICS501, 502, 511, 512, and 525 for clock multipliers.
ICS542
Features
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8-pin SOIC package, Pb free
Available in RoHS compliant package
IDT’s lowest cost clock divider
Low skew (500 ps) outputs. One is /2 of the other
Easy to use with other generators and buffers
Input clock frequency up to 156 MHz
Output clock duty cycle of 45/55
Power-down turns off chip
Output Enable
Advanced, low-power CMOS process
Operating voltage of 3.3 V or 5 V
Does not degrade phase noise - no PLL
Available in industrial and commercial temperature
ranges
Block Diagram
VDD
CLK1
S1, S0
Divider
and
Selection
Circuitry
/2
CLK2
Input Clock
GND
OE (both outputs)
IDT™ / ICS™
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Pin Assignment
I CLK
VDD
GND
S0
1
2
3
4
8
7
6
5
CLK
CLK/ 2
OE
S1
Clock Decoding Table
S1
0
0
1
1
S0
0
1
0
1
CLK
Input/6
Input/8
Input/2
CLK/2
Power Down All
Input/12
Input/16
Input/4
0 = connect directly to ground
1 = connect directly to VDD
8-pin (150 mil) SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
ICLK
VDD
GND
S0
S1
OE
CLK/2
CLK
Pin
Type
XI
Power
Power
Input
Input
Input
Output
Output
Clock input.
Connect to +3.3 V or +5 V.
Pin Description
Connect to ground.
Select 0 for output clock. Connect to GND or VDD, per decoding table above.
Internal pull-up resistor.
Select 1 for output clock. Connect to GND or VDD, per decoding table above.
Internal pull-up resistor.
Output Enable. Tri-states both output clocks when low. Internal pull-up
resistor.
Clock output per table above. Low skew divide by two of pin 8 clock.
Clock output per table above.
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω
.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS542
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
IDT™ / ICS™
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same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS542. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS542. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-40 to +85° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
Min.
0
-40
3.0
Typ.
Max.
+70
+85
5.5
Units
°
C
°
C
V
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DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temp. 0 to +70° C (commercial), -40 to +85° C (industrial)
Parameter
Operating Voltage
Input High Voltage,
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Operating Supply Current
Operating Supply Current
Short Circuit Current
Input Capacitance
Nominal Output Impedance
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
I
DD
I
DD
I
OS
C
IN
Z
O
Conditions
ICLK (pin 1)
ICLK (pin 1)
S0, S1, OE
S0, S1, OE
I
OH
= -25 mA
I
OL
= 25 mA
No Load, 5.0 V,
11 sel
No Load, 3.3 V,
11 sel
S0, S1, OE
at VDD/2
Min.
3.0
VDD/2+1
2
Typ.
VDD/2
VDD/2
Max.
5.5
VDD/2-1
0.8
Units
V
V
V
V
V
V
V
mA
mA
mA
pF
Ω
2.4
0.4
11
7
±40
4
20
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temp. 0 to +70° C (commercial), -40 to +85° C (industrial)
Parameter
Input Frequency, clock input
Input Frequency, clock input
Output Rise Time
Output Fall Time
Duty Cycle
Skew of Output Clocks
Propagation Delay
Symbol
Conditions
VDD = 5 V
VDD = 3.3 V
Min.
0
0
Typ.
Max.
156
156
Units
MHz
MHz
ns
ns
t
OR
t
OF
0.8 to 2.0 V
2.0 to 0.8 V
at VDD/2
rising edges at VDD/2
ICLK to CLK
45
1
1
49 to 51
55
500
15
%
ps
ns
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
150
140
120
40
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
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Package Outline and Package Dimensions
(8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
8
Inches
Min
Max
Symbol
Min
Max
A
A1
E
INDEX
AREA
H
1.35
0.10
0.33
0.19
4.80
3.80
5.80
0.25
0.40
0
°
h x 45
1.75
0.25
0.51
0.25
5.00
4.00
6.20
0.50
1.27
8
°
.0532
.0040
.013
.0075
.1890
.1497
.2284
.010
.016
0
°
.0688
.0098
.020
.0098
.1968
.1574
.2440
.020
.050
8
°
B
C
D
E
e
H
1 2
D
1.27 BASIC
0.050 BASIC
h
L
α
A
A1
C
-C-
e
B
SEATING
PLANE
L
.10 (.004)
C
Ordering Information
Part / Order Number
542MLF
542MLFT
542MILF
542MILFT
Marking
542MLF
542MLF
542MILF
542MILF
Shipping Packaging
Tubes
Tape and Reel
Tubes
Tape and Reel
Package
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™
CLOCK DIVIDER
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ICS542
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