DATASHEET
QUAD OUTPUT SPREAD SPECTRUM CLOCK GENERATOR
Description
The MK1725 generates 4 high-quality, high-frequency
spread spectrum clock outputs. It is designed to replace
spread spectrum clock generators and a buffer in many
digital consumer applications. Using IDT’s patented Phase
Locked Loop (PLL) techniques, the device runs from a lower
frequency clock or crystal input.
The MK1725 has a 16 location ROM table which provides
maximum flexibility for system designers. The chip also has
a power down pin which can be used to reduce power.
MK1725
Features
•
•
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•
•
•
•
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Packaged in 16-pin TSSOP
Available in Pb (lead) free package
Replaces a spread spectrum clock generator and a buffer
Input clock or crystal frequency of 20-34 MHz
Output frequency of 20-136 MHz
Four spread spectrum clock outputs
Duty cycle of 45/55
Operating voltage of 3.3 V
Advanced, low power CMOS process
Available in Commercial (0 to +70°C) and Industrial (-40
to +85°C) temperature ranges
Block Diagram
VDD
3
4
S3:0
PLL/Clock
Synthesis
and
Spread
Spectrum
Circuitry
4
CLK1:4
X1/ICLK
20-34 MHz
crystal or
clock
Crystal
Oscillator
X2
Optional crystal
capacitors.
GND
3
PDTS
IDT™
QUAD OUTPUT SPREAD SPECTRUM CLOCK GENERATOR
1
MK1725
REV G 033109
MK1725
QUAD OUTPUT SPREAD SPECTRUM CLOCK GENERATOR
SSCG
Pin Assignment
X1
S0
S3
VDD
GND
S1
CLK1
CLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
VDD
PDTS
S2
VDD
GND
CLK4
CLK3
CLK Output Selection Table
S3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
1
0
1
1
0
0
1
0
1
0
1
1
0
0
1
S0
Multiplier
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
2
2
2
2
4
4
4
4
1
2
4
TEST
CLK1:4
Spread %
-1%
-0.5%
+/- 0.5%
+/- 0.25%
-1%
-0.5%
+/- 0.5%
+/- 0.25%
-1%
-0.5%
+/- 0.5%
+/- 0.25%
OFF
OFF
OFF
TEST
16 pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
Pin
Name
X1
S0
S3
VDD
GND
S1
CLK1
CLK2
CLK3
Pin
Type
Input
Input
Input
Power
Power
Input
Output
Output
Output
Pin Description
Connect to a 20 to 34 MHz crystal or clock input.
Select pin 0. Determines frequency and spread amount on
output clocks as per table above. Internal pull-down.
Select pin 3. Determines frequency and spread amount on
output clocks as per table above. Internal pull-down.
Connect to +3.3 V.
Connect to ground.
Select pin 1. Determines frequency and spread amount on
output clocks as per table above. Internal pull-down.
Clock 1 output. Frequency and spread amount are determined
by table above. Weak internal pull-down when tri-state.
Clock 2 output. Frequency and spread amount are determined
by table above. Weak internal pull-down when tri-state.
Clock 3 output. Frequency and spread amount are determined
by table above. Weak internal pull-down when tri-state.
IDT™
QUAD OUTPUT SPREAD SPECTRUM CLOCK GENERATOR
2
MK1725
REV G 033109
MK1725
QUAD OUTPUT SPREAD SPECTRUM CLOCK GENERATOR
SSCG
Pin
Number
10
11
12
13
14
15
16
Pin
Name
CLK4
GND
VDD
S2
Pin
Type
Output
Power
Power
Input
Pin Description
Clock 4 output. Frequency and spread amount are determined
by table above. Weak internal pull-down when tri-state.
Connect to ground.
Connect to +3.3 V.
Select pin 2. Determines frequency and spread amount on
output clocks as per table above. Internal pull-down.
Power Down Tri-state. Powers down entire chip and tri-states
outputs when low. Internal pull-up resistor.
Connect to +3.3V.
20 MHz to 34 MHz crystal input. Float for clock input.
PDTS
VDD
X2
Input
Power
Input
External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the MK1725
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitors should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitors and VDD pins. The PCB trace to VDD pins
should be kept as short as possible, as should the PCB
trace to the ground via.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI the 33
Ω
series termination resistor (if
needed) should be placed close to the clock outputs.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
MK1725. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
Ω
trace (a commonly
used trace impedance), place a 33
Ω
resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20
Ω
.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-6)*2. In this equation, C
L
= crystal load capacitance in pF.
Example: For a crystal with an 18 pF load capacitance, each
crystal capacitor would be 24 pF [(18-6) x 2 = 24].
IDT™
QUAD OUTPUT SPREAD SPECTRUM CLOCK GENERATOR
3
MK1725
REV G 033109
MK1725
QUAD OUTPUT SPREAD SPECTRUM CLOCK GENERATOR
SSCG
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1725. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
Junction Temperature
Soldering Temperature
5V
Rating
-0.5 V to VDD+0.5 V
0 to +70
°
C
-40 to +85
°
C
-65 to +150
°
C
125
°
C
260
°
C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
Min.
0
-40
+3.135
Typ.
Max.
+70
+85
Units
°
C
°
C
+3.3
+3.465
V
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%
, T
A
= 0 to +70
°
C (commercial), -40 to +85°C (industrial)
Parameter
Operating Voltage
Supply Current
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
Input Capacitance
Nominal Output Impedance
Internal Pull-up Resistor
Symbol
VDD
IDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OH
V
OL
I
OS
C
IN
Z
OUT
R
PU
Conditions
20M in S3:0=[0100]
Input selects
Input selects
ICLK
ICLK
I
OH
= -4 mA
I
OH
= -12 mA
I
OL
= 12 mA
Clock outputs
Min.
3.135
2
Typ.
3.3
22
Max.
3.465
Units
V
mA
V
0.8
VDD/2+1
VDD/2-1
VDD-0.4
2.4
0.4
±70
5
20
V
V
V
V
V
V
mA
pF
Ω
PDTS pin
360
k
Ω
IDT™
QUAD OUTPUT SPREAD SPECTRUM CLOCK GENERATOR
4
MK1725
REV G 033109
MK1725
QUAD OUTPUT SPREAD SPECTRUM CLOCK GENERATOR
SSCG
Parameter
Internal Pull-down Resistor
Symbol
R
PD
Conditions
Clock outputs; S3:0
Min.
Typ.
510
Max.
Units
k
Ω
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%
, T
A
= 0 to +70
°
C (commercial), -40 to +85°C (industrial)
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Symbol
f
IN
t
OR
t
OF
Conditions
Crystal or clock input
20% to 80%, Note 1
80% to 20%, Note 1
At VDD/2, Note 1
1X, 2X modes
at VDD/2, Note 1
4X mode
Min.
20
Typ.
1.2
1.0
Max. Units
34
MHz
ns
ns
55
60
%
%
ps
50
250
kHz
ps
ms
ns
45
40
50
50
150
Absolute Clock Period Jitter
Modulation Frequency
Output to Output Skew
Output Enable Time
Output Disable Time
Note 1: Measured with a 15 pF load.
t
J
f
mod
Cycle to cycle, Note 1
25
Non-spread modes
PDTS high to output
spread profile stable
PDTS low to tri-state
t
OE
t
OD
2.6
10
IDT™
QUAD OUTPUT SPREAD SPECTRUM CLOCK GENERATOR
5
MK1725
REV G 033109
stm32/stm8
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