19-2858; Rev 2; 2/94
8 x 8 Video Crosspoint Switch
_______________General Description
The MAX456 is the first monolithic CMOS 8 x 8 video
crosspoint switch that significantly reduces component
count, board space, and cost. The crosspoint switch
contains a digitally controlled matrix of 64 T-switches
that connect eight video input signals to any, or all, out-
put channels. Each matrix output connects to eight
internal, high-speed (250V/µs), unity-gain-stable buffers
capable of driving 400Ω and 20pF to ±1.3V. For appli-
cations requiring increased drive capability, the
MAX456 outputs can be connected directly to two
MAX470 quad, gain-of-two video buffers, which are
capable of driving 75Ω loads.
Three-state output capability and internal, programma-
ble active loads make it feasible to parallel multiple
MAX456s and form larger switch matrices.
In the 40-pin DIP package, crosstalk (70dB at 5MHz) is
minimized, and board area and complexity are simpli-
fied by using a straight-through pinout. The analog
inputs and outputs are on opposite sides, and each
channel is separated by a power-supply line or quiet
digital logic line.
____________________________Features
o
o
o
o
o
o
Routes Any Input Channel to Any Output Channel
Switches Standard Video Signals
Serial or Parallel Digital Interface
Expandable for Larger Switch Matrices
80dB All-Channel Off Isolation at 5MHz
8 Internal Buffers with:
250V/µs Slew Rate, Three-State Output Capability,
Power-Saving Disable Feature, 35MHz Bandwidth
MAX456
______________Ordering Information
PART
MAX456CPL
MAX456CQH
MAX456C/D
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
40 Plastic DIP
44 PLCC
Dice*
Ordering Information continued on last page.
* Dice are specified at T
A
= +25°C, DC parameters only.
_________________Pin Configurations
TOP VIEW
D1/SER OUT
1
D0/SER IN
2
A2
3
A1
4
IN0
5
A0
6
40
V+
39
OUT0
38
D2
________________________Applications
Video Test Equipment
Video Security Systems
Video Editing
MAX456
37
OUT1
36
D3
35
OUT2
34
V-
33
OUT3
32
AGND
31
OUT4
30
AGND
29
OUT5
28
AGND
27
OUT6
26
V+
25
OUT7
24
CE
23
CE
22
LATCH
21
WR
________Typical Application Circuit
8 INPUT CHANNELS
IN1
7
MAX470
A
V
= 2
WR
LATCH
LOAD
8
75Ω
IN2
9
DGND
10
75Ω
IN3
11
DGND
12
IN4
13
MAX456
OUTPUT
SELECT
A2
A1
A0
8X8
T-SWITCH
MATRIX
D3
D2
D1/SER OUT
D0/SER IN
A
V
= 2
EDGE/LEVEL
14
IN5
15
V+
16
IN6
17
SER/PAR
18
IN7
19
V-
20
INPUT
SELECT
OR
SERIAL
I/O
MAX470
PLCC on last page
DIP
1
________________________________________________________________
Maxim Integrated Products
Call toll free 1-800-998-8800 for free samples or literature.
8 x 8 Video Crosspoint Switch
MAX456
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (V+ to V-) ...........................................+12V
Positive Supply Voltage V+ Referred to AGND......-0.3V to +12V
Negative Supply Voltage V- Referred to AGND .....-12V to +0.3V
DGND Voltage.........................................................AGND ±0.3V
Buffer Short Circuit to Ground when
Not Exceeding Package Power Dissipation .............Indefinite
Analog Input Voltage ............................(V+ + 0.3V) to (V- - 0.3V)
Digital Input Voltage .............................(V+ + 0.3V) to (V- - 0.3V)
Input Current, Power On or Off
Digital Inputs.................................................................±20mA
Analog Inputs ...............................................................±50mA
Continuous Power Dissipation (T
A
= +70°C)
40-Pin Plastic DIP (derate 11.3mW/°C above +70°C)....889mW
40-Pin CERDIP (derate 20.0mW/°C above +70°C)....1600mW
44-Pin PLCC (derate 13.3mW/°C above +70°C) .......1066mW
Operating Temperature Ranges:
MAX456C _ _ ......................................................0°C to +70°C
MAX456E _ _ ...................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10 sec) ............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
PARAMETER
Input Voltage Range
Voltage Gain
(V+ = 5.0V, V- = -5.0V, -1.3V
≤
V
IN
≤
+1.3V; LOAD = +5V; internal load resistors on; AGND = DGND = 0V; T
A
= +25°C,
unless otherwise noted.)
CONDITIONS
Internal load
resistors on, no
external load,
V
IN
= 0V to 1V
T
A
= +25°C
T
A
= T
MIN
to T
MAX
T
A
= T
MIN
to T
MAX
±4.5
T
A
= +25°C
T
A
= T
MIN
to T
MAX
T
A
= +25°C
T
A
= T
MIN
to T
MAX
±4.5V to ±5.5V, DC measurement
T
A
= T
MIN
to T
MAX
Internal load resistors off, all buffers
off, T
A
= T
MIN
to T
MAX
T
A
= +25°C
T
A
= T
MIN
to T
MAX
Internal load resistors on, no external load
T
A
= T
MIN
to T
MAX
10
0.8
2.4
Serial mode,
–—
—–
SER/PAR = 5V
I
OL
= 1.6mA
I
OH
= -0.4mA
4
0.4
50
64
±0.1
±10
±100
250
200
±1.3
±1
400
600
765
1.5
39
20
±5.5
45
60
3.0
4
MIN
-1.3
0.99
0.98
TYP
MAX
1.3
1.01
V/V
T
A
= T
MIN
to T
MAX
1.0
1.02
±7
±12
mV
µV/°C
V
mA
mA
dB
nA
nA
Ω
V
µA
Ω
V
V
V
UNITS
V
T
A
= +25°C
1.0
Buffer Offset Voltage
Offset Voltage Drift
Operating Supply Voltage
Supply Current, All Buffers On
(No External Load)
Supply Current, All Buffers Off
Power-Supply Rejection Ratio
Analog Input Current
Output Leakage Current
Internal Amplifier Load Resistor
(LOAD Pin = 5V)
Buffer Output Voltage Swing
Digital Input Current
Output Impedance at DC
Input Logic Low Threshold
Input Logic High Threshold
SER OUT Output Logic Low
SER OUT Output Logic High
2
_______________________________________________________________________________________
8 x 8 Video Crosspoint Switch
ELECTRICAL CHARACTERISTICS
(V+ = 5.0V, V- = -5.0V, -1.3V
≤
V
IN
≤
+1.3V, LOAD = +5V, internal load resistors on, AGND = DGND = 0V, T
A
= +25°C,
unless otherwise noted.)
PARAMETER
DYNAMIC SPECIFICATIONS
(Note 1)
X
Output-Buffer Slew Rate
Single-Channel Crosstalk
All-Channel Crosstalk
All-Channel Off Isolation
-3dB Bandwidth
Differential Phase Error
Differential Gain Error
Input Noise
Input Capacitance
Buffer Input Capacitance
Output Capacitance
CONDITIONS
Internal load resistors on, 10pF load
5MHz, V
IN
= 2V
P-P
(Note 2)
5MHz, V
IN
= 2V
P-P
(Notes 2, 3)
5MHz, V
IN
= 2V
P-P
(Note 2)
10pF load, V
IN
= 2V
P-P
(Note 2)
(Note 4)
(Note 4)
DC to 40MHz
All buffer inputs grounded
Additional capacitance for each out-
put buffer connected to channel input
Output buffer off
25
60
MIN
TYP
250
70
57
80
35
1.0
0.5
0.3
6
2
7
1.0
MAX
UNITS
V/µs
dB
dB
dB
MHz
deg
%
mV
RMS
pF
pF
pF
MAX456
SWITCHING CHARACTERISTICS
(Note 1)
(Figure 4, V+ = 5.0V, V- = -5.0V, -1.3V
≤
V
IN
≤
+1.3V, LOAD = +5V, internal load resistors on, AGND = DGND = 0V,
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
Chip-Enable to Write Setup
Write Pulse Width High
Write Pulse Width Low
Data Setup
Data Hold
Latch Pulse Width
Latch Delay
Switch Break-Before-Make Delay
LATCH Edge to Switch Off
LATCH Edge to Switch On
Note 1:
Note 2:
Note 3:
Note 4:
SYMBOL
t
CE
t
WH
t
WL
t
DS
t
DH
t
L
t
D
t
ON -
t
OFF
t
OFF
t
ON
LATCH on
Parallel mode
32-bit serial mode
CONDITIONS
MIN
0
80
80
240
160
0
80
80
15
35
50
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Guaranteed by design.
See
Dynamic Test Circuits
on page 11.
3dB typical crosstalk improvement when R
S
= 0Ω.
Input test signal: 3.58MHz sine wave of amplitude 40IRE superimposed on a linear ramp (0 to 100IRE). IRE is a unit of
video-signal amplitude developed by the International Radio Engineers. 140IRE = 1.0V.
_______________________________________________________________________________________
3
8 x 8 Video Crosspoint Switch
MAX456
______________________________________________________________Pin Description
PIN
DIP
—
1
2
3, 4, 6
5, 7, 9, 11,
13, 15, 17, 19
8
PLCC
1, 12, 23, 34
2
3
4, 5, 7
6, 8, 10, 13,
15, 17, 19, 21
9
NAME
N.C.
D1/SER OUT
D0/SER IN
A2, A1, A0
IN0–IN7
FUNCTION
No connect. Not internally connected.
—–
—
Parallel Data Bit D1 when SER/PAR = 0V. Serial Output for cascading
—–
—
multiple parts when SER/PAR = 5V.
—–
—
Parallel Data Bit D0 when SER/PAR = 0V. A Serial Input when
—–
—
SER/PAR = 5V.
Output Buffer Address Lines
Video lnput Lines
Asynchronous control line. When LOAD = 1, all the 400Ω internal active
loads are on. When LOAD = 0, external 400Ω loads must be used. The
buffers MUST have a resistive load to maintain stability.
Digital Ground Pins. Both DGND pins must have the same potential and
be bypassed to AGND. DGND should be within ±0.3V of AGND.
When this control line is high, the 2nd-rank registers are loaded with the
rising edge of the LATCH line. If this control line is low, the 2nd-rank reg-
isters are transparant when LATCH is low, passing data directly from the
1st-rank registers to the decoders.
All V+ pins must be tied to each other and bypassed to AGND
separately (Figure 2).
5V = 32-Bit Serial, 0V = 7-Bit Parallel
Both V- pins must be tied to each other and bypassed to AGND
separately (Figure 2).
WRITE in the serial mode, shifts data in. In the parallel mode, WR loads
data into the 1st-rank registers. Data is latched on the rising edge.
–— —
— —–
If EDGE/LEVEL = 5V, data is loaded from the 1st-rank registers to the 2nd-
–— —
— —–
rank registers on the rising edge of LATCH. If EDGE/LEVEL = 0V, data is
loaded while LATCH = 0V. In addition, data is loaded during the execution
of parallel-mode functions 1011 through 1110, or if LATCH = 5V during the
execution of the parallel-mode "software-LATCH" command (1111).
– ——— ——
— ———
—
–
––
—
Chip Enable. When CE = 0V and CE = 5V, the WR line is enabled.
––
—
Chip Enable. When CE = 0V and CE = 5V, the WR line is enabled.
Output Buffers 7-0 (Note 1)
Analog Ground must be at 0.0V since the gain resistors of the buffers are
tied to these 3 pins.
–—
—–
Parallel Data Bit D3 when SER/ PAR = 0V. When D3 = 0V, D0-D2 specifies
the input channel to be connected to buffer. When D3 = 5V, then D0-D2
–—
—–
specify control codes. D3 is not used when SER/ PAR = 5V.
–—
—–
Parallel Data Bit D2 when SER/ PAR = 0V. Not used when
–—
—–
SER/ PAR = 5V.
LOAD
10, 12
11, 14
DGND
14
16
–— —
— —–
EDGE/LEVEL
16, 26, 40
18
20, 34
21
18, 29, 44
20
22, 38
24
V+
—–
—
SER/PAR
V-
WR
22
25
LATCH
23
24
25, 27, 29, 31,
33, 35, 37, 39
28, 30, 32
26
27
28, 30, 32, 35,
37, 39, 41, 43
31, 33, 36
—
–
CE
CE
OUT7-OUT0
AGND
36
40
D3
38
42
D2
Note 1:
Buffer inputs are internally grounded with a 1000 or 1001 command from the D3-D0 lines. AGND must be at 0.0V since the
gain setting resistors of the buffers are internally tied to AGND.
4
_______________________________________________________________________________________
8 x 8 Video Crosspoint Switch
_______________Detailed Description
Output Buffers
The MAX456 video crosspoint switch consists of 64
T-switches in an 8 x 8 grid (Figure 1). The 8 matrix out-
puts are followed by 8 wideband buffers optimized for
driving 400Ω and 20pF loads. Each buffer has an
internal active load on the output that can be readily
shut off via the LOAD input (off when LOAD = 0V). The
shut-off is useful when two or more MAX456 circuits are
connected in parallel to create more input channels.
With more input channels, only one set of buffers can
be active and only one set of loads can be driven.
And, when active, the buffer must have either
1) an internal load, 2) the internal load of another buffer
in another MAX456, or 3) an external load.
Each MAX456 output can be disabled under logic con-
trol. When a buffer is disabled, its output enters a high-
impedance state. In multichip parallel applications, the
disable function prevents inactive outputs from loading
lines driven by other devices. Disabling the inactive
buffers reduces power consumption.
The MAX456 outputs connect easily to MAX470 quad,
gain-of-two buffers when 75Ω loads must be driven.
___________________Digital Interface
The desired switch state can be loaded in a 7-bit paral-
lel-interface mode or 32-bit serial-interface mode (see
Table 3 and Figures 4-6). All action associated with the
WR line occurs on its rising — –
– —edge. The same is true for
— —
the LATCH line if EDGE/LEVEL is high. Otherwise, the
second-rank– registers update while LATCH is low
— —–
——
(when EDGE/LEVEL is low). WR is logically ANDed with
–—
–
CE and C E to allow active-high or active-low chip
enable.
MAX456
7-Bit Parallel Mode
In the parallel-interface mode, the 7 data bits A2-A0
and D3-D0 specify an output channel (A2-A0) and the
input channel to which it connects (D3-D0). The data is
loaded on the rising edge of WR. The 8 input channels
are selected by 0000 through 0111 (D3-D0). The
remaining 8 codes (1000-1111) control other MAX456
functions, as listed in Table 1.
–—
—–
In serial mode (SER/PAR = high), all first-rank registers
are loaded with data, making it unnecessary to specify
an output address (A2, A1, A0). The input data format
is D3-D0, starting with OUT0 and ending with OUT7 for
32 total bits. Only codes 0000 through 1010 are valid.
Code 1010 disables a buffer, while code 1001 enables
it. After data is shifted into the 32-bit first-rank register,
it is transferred to the second rank by the LATCH line
(see Table 2).
32-Bit Serial-Interface Mode
Power-On RESET
The MAX456 has an internal power-on reset (POR) cir-
cuit that remains low for 5µs when power is applied.
POR also remains low if the total supply voltage is less
than 4V.
The POR disables all buffer outputs at
power-up,
but the switch matrix is not preset to any ini-
tial condition. The desired switch state should be pro-
grammed before the buffer outputs are enabled.
_______________________________________________________________________________________
5
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