February 2007
®
AS6C2008
Rev. 1.1
256K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The AS6C2008 is a 2,097,152-bit low power CMOS
static random access memory organized as 262,144
words by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
The AS6C2008 is well designed for very low power
system applications, and particularly well suited for
battery back-up nonvolatile memory application.
The AS6C2008 operates from a single power
supply of 2.7V ~ 3.6V
.
FEATURES
Access time : 55ns
Low power consumption:
Operating current :20mA (TYP.)
Standby current : 20mA(TYP.)L Version
1µ
A (TYP.) LL-version
Single 2.7V ~ 3.6V power supply
Fully static operation
Tri-state output
Data retention voltage : 1.5V (MIN.)
All Products ROHS Compliant
Package : 32-pin 450 mil SOP
32-pin 8mm x 20mm TSOP-I
32-pin 8mm x 13.4mm sTSOP
36-ball 6mm x 8mm TFBGA
PRODUCT FAMILY
Product
Family
Operating
Temperature
Vcc Range
Speed
Power Dissipation
Standby(I
SB1,
TYP.) Operating(Icc,TYP.)
AS6C2008 (I)
-40 ~ 85ºC
2
.7 ~ 3.6V
55ns
20µA(L)/1µA(LL)
20mA
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
A0 - A17
DQ0 – DQ7
CE#, CE2
WE#
OE#
V
CC
V
SS
NC
Vcc
Vss
A0-A17
DECODER
256Kx8
MEMORY ARRAY
DQ0-DQ7
I/O DATA
CIRCUIT
COLUMN I/O
CE#
CE2
WE#
OE#
CONTROL
CIRCUIT
10/February/07, v.1.0
Alliance Memory Inc.
Page 1 of 13
February 2007
®
AS6C2008
Rev. 1.1
256K X 8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE#
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A11
A9
A8
A13
WE#
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
AS6C2008
AS6C2008
TSOP-I/sTSOP
A
B
C
D
E
F
G
H
A0
DQ4
DQ5
Vss
Vcc
DQ6
A1
A2
CE2
WE#
NC
A3
A4
A5
A6
A7
A8
DQ0
DQ1
Vcc
Vss
NC
A17
DQ2
A15 DQ3
A13
A14
DQ7 OE# CE# A16
A9
A10
A11
A12
1
2
3
4
TFBGA
5
6
10/February/07, v.1.0
Alliance Memory Inc.
Page 2 of 13
February 2007
®
AS6C2008
Rev. 1.1
256K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
T
SOLDER
-40 to 85(I grade)
-65 to 150
1
50
260
RATING
-0.5 to 4.6
UNIT
V
ºC
ºC
W
mA
ºC
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE#
H
X
L
L
L
CE2
X
L
H
H
H
OE#
X
X
H
L
X
WE#
X
X
H
H
L
I/O OPERATION
High-Z
High-Z
High-Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB
,I
SB1
I
SB
,I
SB1
I
CC
,I
CC1
I
CC
,I
CC1
I
CC
,I
CC1
H = V
IH
, L = V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
PARAMETER
Supply Voltage
V
CC
*1
Input High Voltage
V
IH
*2
Input Low Voltage
V
IL
Input Leakage Current
I
LI
V
CC
≧
V
IN
≧
V
SS
V
CC
≧
V
OUT
≧
V
SS,
Output Leakage
I
LO
Current
Output Disabled
Output High Voltage
V
OH
I
OH
= -1mA
Output Low Voltage
V
OL
I
OL
= 2mA
Cycle time = Min.
I
CC
CE# = V
IL
and CE2 = V
IH
, - 55
I
I/O
= 0mA
Average Operating
Cycle time = 1µs
Power supply Current
CE#
≦
0.2V and CE2
≧
V
CC
-0.2V,
I
CC1
I
I/O
= 0mA
other pins at 0.2V or V
CC
-0.2V
I
SB
CE# = V
IH
or CE2 = V
IL
-
Standby Power
CE#
≧
V
CC
-0.2V
Supply Current
I
SB1
-
or CE2
≦
0.2V
-I*
*I= Industrial temperature
MIN.
2.7
2.2
- 0 .2
-1
-1
2.2
-
-
TYP.
3.0
-
-
-
-
2.7
-
20
*4
MAX.
3.6
V
CC
+0.3
0.6
1
1
-
0.4
35
UNIT
V
V
V
µA
µA
V
V
mA
-
-
4
0.3
5
0.5
mA
mA
-
1
20
*5
µA
10/February/07, v.1.0
Alliance Memory Inc.
Page 3 of 13
February 2007
®
AS6C2008
Rev. 1.1
256K X 8 BIT LOW POWER CMOS SRAM
Notes:
1. V
IH
(max) = V
CC
+ 3.0V for pulse width less than 10ns.
2. V
IL
(min) = V
SS
- 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at V
CC
= V
CC
(TYP.) and T
A
= 25
ºC
5. 10µA for special request
CAPACITANCE
(T
A
= 25
℃
, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
Note : These parameters are guaranteed by device characterization, but not production tested.
-
-
MAX
6
8
UNIT
pF
pF
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to V
CC
- 0.2V
3ns
1.5V
C
L
= 30pF + 1TTL, I
OH
/I
OL
= -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
SYM
t
RC
t
AA
t
ACE
t
OE
t
CLZ
*
t
OLZ
*
t
CHZ
*
t
OHZ
*
t
OH
SYM
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
*
t
WHZ
*
AS6C2008-55
MIN MAX.
55
-
-
55
-
55
-
30
10
-
5
-
-
20
-
20
10
-
AS6C2008-55
MIN
MAX.
55
-
50
-
50
-
0
-
45
-
0
-
25
-
0
-
5
-
-
20
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
10/February/07, v.1.0
Alliance Memory Inc.
Page 4 of 13
February 2007
®
AS6C2008
Rev. 1.1
256K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled) (1,2)
t
RC
Address
t
AA
Dout
Previous Data Valid
t
OH
Data Valid
READ CYCLE 2
(CE# and CE2 and OE# Controlled) (1,3,4,5)
t
RC
Address
t
AA
CE#
t
ACE
CE2
OE#
t
OLZ
t
OE
t
OH
t
OHZ
t
CHZ
Data Valid
High-Z
t
CLZ
Dout
High-Z
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low
.,
CE2 = high
.
3.Address must be valid prior to or coincident with CE# = low
,
CE2 = high; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
= 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ.
10/February/07, v.1.0
Alliance Memory Inc.
Page 5 of 13
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