Differential-to-HCSL Differential
PCI EXPRESS™ Jitter Attenuator
General Description
The ICS871004I-04 is a high performance Jitter Attenuator designed
for use in PCI Express™ systems. In some PCI Express systems,
such as those found in desktop PCs, the PCI Express clocks are
generated from a low bandwidth, high phase noise PLL frequency
synthesizer. In these systems, a jitter attenuator may be required to
attenuate high frequency random and deterministic jitter components
from the PLL synthesizer and from the system board. The
ICS871004I-04 has three PLL bandwidth modes: 200kHz, 700kHz
and 1700kHz. The 200kHz mode provides the maximum jitter
attenuation, but it also results in higher PLL tracking time. In this
mode, the spread spectrum modulation may also be attenuated. The
700kHz bandwidth provides an intermediate bandwidth that can
easily track tri-angular spread profiles, while providing good jitter
attenuation. The 1700kHz bandwidth provides the best tracking skew
and will pass most spread profiles, but the jitter attenuation will not be
as good as the lower bandwidth modes. The ICS871004I-04 can be
set for different modes using the F_SELx pins as shown in Table 3C.
The ICS871004I-04 uses IDT’s 3
RD
Generation FemtoClock
®
PLL
technology to achieve the lowest possible phase noise. The device is
packaged in a 24 Lead TSSOP package, making it ideal for use in
space constrained applications such as PCI Express add-in cards.
ICS871004I-04
DATA SHEET
Features
•
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Four differential HCSL output pairs
One differential clock input
CLK, nCLK can accept the following differential input levels:
LVPECL, LVDS, HSTL, HCSL
Output frequency range: 98MHz to 640MHz
Input frequency range: 98MHz to 128MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 7.5ps (typical)
Three bandwidth modes allow the system designer to make jitter
attenuation/tracking skew design trade-offs
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
PLL Bandwidth (typical) Table
BW_SEL[1:0]
00 = PLL Bandwidth: ~200kHz
01 = PLL Bandwidth: ~700kHz (default)
10 = PLL Bandwidth: ~1700kHz
11 = PLL BYPASS
Block Diagram
IREF
OE
F_SEL[1:0]
BW_SEL[1:0]
Pullup
Pin Assignment
nQ0
nQ2
Q2
V
DD
IREF
GND
MR
BW_SEL0
V
DDA
F_SEL0
V
DD
OE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q0
V
DD
Q1
nQ1
Q3
nQ3
BW_SEL1
F_SEL1
GND
GND
nCLK
CLK
Pulldown
PU:PD
2
2
Control
Logic
Q0
nQ0
CLK
nCLK
Pulldown
Pullup
Phase
Detector
VCO
490 - 640MHz
M
U
X
0 0 ÷5
(default)
Q1
nQ1
0 1 ÷4
1 0 ÷2
1 1 ÷1
ICS871004I-04
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
Q2
nQ2
Q3
÷5
nQ3
MR
Pulldown
ICS871004AGI-04I REVISION A SEPTEMBER 5, 2012
1
©2012 Integrated Device Technology, Inc.
ICS871004I-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Table 1. Pin Descriptions
Number
1, 24
2, 3
4, 11, 23
5
6, 15, 16
Name
nQ0, Q0
nQ2, Q2
V
DD
IREF
GND
Output
Output
Power
Input
Power
Type
Description
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Core supply pins.
An external fixed precision resistor (475
Ω
) from this pin to ground provides a
reference current used for differential current-mode Qx, nQx clock outputs.
Power supply ground.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs (Qx) to go low and the inverted outputs (nQx) to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Selects the PLL Bandwidth input.
Analog supply pin.
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Frequency select pins.LVCMOS/LVTTL interface levels
Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are
in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A.
Non-inverting differential clock input.
Inverting differential clock input.
Selects the PLL Bandwidth input.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
7
MR
Input
Pulldown
8
9
10,
17
12
13
14
18
19, 20
21, 22
BW_SEL0
V
DDA
F_SEL0,
F_SEL1
OE
CLK
nCLK
BW_SEL1
nQ3, Q3
nQ1, Q1
Input
Power
Input
Input
Input
Input
Input
Output
Output
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS871004AGI-04I REVISION A SEPTEMBER 5, 2012
2
©2012 Integrated Device Technology, Inc.
ICS871004I-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Function Tables
Table 3A. Output Enable Function Table
Input
OE
0
1 (default)
Q[0:3]
High-Impedance
Enabled
Outputs
nQ[0:3]
High-Impedance
Enabled
Table 3B. PLL Bandwidth Control Table
Input
BW_SEL1
0
0
1
1
BW_SEL0
0
1
0
1
PLL Bandwidth
~200kHz
~700kHz (default)
~1700kHz
PLL BYPASS
Table 3C. F_SELx Function Table
Inputs
Input Frequency (MHz)
100
100
100
100
F_SEL1
0
0
1
1
F_SEL0
0
1
0
1
Divider Value
÷5
÷4
÷2
÷1
Output Frequency (MHz)
100 (default)
125
250
500
ICS871004AGI-04I REVISION A SEPTEMBER 5, 2012
3
©2012 Integrated Device Technology, Inc.
ICS871004I-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
82.3°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.10
Typical
3.3
3.3
40
6.4
Maximum
3.465
V
DD
55
10
Units
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
Parameter
MR, OE,
F_SEL[1:0]
BW_SEL[1:0]
MR, OE,
F_SEL[1:0]
BW_SEL[1:0]
BW_SEL0
OE, F_SEL1
I
IH
Input High Current
F_SEL[1:0],
MR, BW_SEL1
BW_SEL0
OE, F_SEL1
I
IL
Input Low Current
F_SEL[1:0],
MR, BW_SEL1
V
DD
= 3.465V, V
IN
= 0V
-5
µA
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-150
150
µA
µA
V
DD
= V
IN
= 3.465V
Test Conditions
Minimum
2
V
DD
– 0.3
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.3
5
Units
V
V
V
V
µA
V
IH
Input High Voltage
V
IL
Input Low Voltage
ICS871004AGI-04I REVISION A SEPTEMBER 5, 2012
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©2012 Integrated Device Technology, Inc.
ICS871004I-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Table 4C. Differential DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
CLK
Input High Current
nCLK,
CLK
I
IL
V
PP
V
CMR
Input Low Current
nCLK
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Table 5A. PCI Express Jitter Specifications,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
t
j
(PCIe Gen 1)
t
REFCLK_HF_RMS
(PCIe Gen 2)
t
REFCLK_LF_RMS
(PCIe Gen 2)
t
REFCLK_RMS
(PCIe Gen 3)
Parameter
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
Phase Jitter RMS;
NOTE 2, 4
Phase Jitter RMS;
NOTE 2, 4
Phase Jitter RMS;
NOTE 3, 4
Test Conditions
ƒ = 100MHz,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ = 100MHz,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
ƒ = 100MHz,
Low Band: 10kHz - 1.5MHz
ƒ = 100MHz,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
Minimum
Typical
32.4
Maximum
50.1
PCIe Industry
Specification
86
Units
ps
1.29
2.33
3.1
ps
1.37
2.14
3.0
ps
0.419
0.619
0.8
ps
NOTE:
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions. For additional information, refer to the
PCI Express Application Note section
in the
datasheet.
NOTE:
PCIe jitter parameters were obtained with Spread Spectrum Modulation disabled.
NOTE 1:
Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 10
6
clock periods.
NOTE 2:
RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t
REFCLK_HF_RMS
(High Band) and 3.0ps RMS for t
REFCLK_LF_RMS
(Low Band).
NOTE 3:
RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the
PCI Express
Base Specification Revision 0.7, October 2009
and is subject to change pending the final release version of the specification.
NOTE 4:
This parameter is guaranteed by characterization. Not tested in production.
ICS871004AGI-04I REVISION A SEPTEMBER 5, 2012
5
©2012 Integrated Device Technology, Inc.
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