without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
04/15/05
1
IS42VS16100C1
PIN FUNCTIONS
Pin No.
20 to 24
27 to 32
Symbol
A0-A10
Type
Input Pin
Function (In Detail)
ISSI
®
A0 to A10 are address inputs. A0-A10 are used as row address inputs during active
command input and A0-A7 as column address inputs during read or write command
input. A10 is also used to determine the precharge mode during other commands. If
A10 is LOW during precharge command, the bank selected by A11 is precharged,
but if A10 is HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts
automatically after the burst access.
These signals become part of the OP CODE during mode register set command
input.
A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when
high, bank 1 is selected. This signal becomes part of the OP CODE during mode
register set command input.
CAS,
in conjunction with the
RAS
and
WE,
forms the device command. See the
“Command Truth Table” item for details on device commands.
The CKE input determines whether the CLK input is enabled within the device. When
is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW,
invalid. When CKE is LOW, the device will be in either the power-down mode, the
clock suspend mode, or the self refresh mode. The CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The
CS
input determines whether command input is enabled within the device.
Command input is enabled when
CS
is LOW, and disabled with
CS
is HIGH. The
device remains in the previous state when
CS
is HIGH.
DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go
to the HIGH impedance state when LDQM/UDQM is HIGH. This function
corresponds to
OE
in conventional DRAMs. In write mode, LDQM and UDQM control
the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is
enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input
data is masked and cannot be written to the device.
RAS,
in conjunction with
CAS
and
WE,
forms the device command. See the
“Command Truth Table” item for details on device commands.
WE,
in conjunction with
RAS
and
CAS,
forms the device command. See the
“Command Truth Table” item for details on device commands.
VDDQ is the output buffer power supply.
VDD is the device internal power supply.
GNDQ is the output buffer ground.
GND is the device internal ground.
19
A11
Input Pin
16
34
CAS
CKE
Input Pin
Input Pin
35
18
CLK
CS
Input Pin
Input Pin
2, 3, 5, 6, 8, 9, 11
12, 39, 40, 42, 43,
45, 46, 48, 49
14, 36
DQ0 to
DQ15
LDQM,
UDQM
DQ Pin
Input Pin
17
15
7, 13, 38, 44
1, 25
4, 10, 41, 47
26, 50
RAS
WE
VDDQ
VDD
GNDQ
GND
Input Pin
Input Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
04/15/05
IS42VS16100C1
FUNCTIONAL BLOCK DIAGRAM
ISSI
®
COMMAND
DECODER
&
CLOCK
GENERATOR
ROW DECODER
CLK
CKE
CS
RAS
CAS
WE
A11
MODE
REGISTER
11
11
ROW
ADDRESS
BUFFER
MEMORY CELL
ARRAY
2048
11
BANK 0
LDQM,
UDQM
SENSE AMP I/O GATE
A10
8
COLUMN
ADDRESS BUFFER
BURST COUNTER
COLUMN
ADDRESS LATCH
DATA IN
BUFFER
16
16
256
COLUMN DECODER
ROW DECODER
MULTIPLEXER
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
REFRESH
CONTROLLER
SELF
REFRESH
CONTROLLER
DQ 0-15
8
256
SENSE AMP I/O GATE
REFRESH
COUNTER
DATA OUT
BUFFER
16
16
11
ROW
ADDRESS
LATCH
11
ROW
ADDRESS
BUFFER
2048
MEMORY CELL
ARRAY
VDD/VDDQ
GND/GNDQ
BANK 1
11
S16BLK.eps
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
04/15/05
3
IS42VS16100C1
ISSI
Rating
–0.5 to +2.6
–0.5 to +2.6
–0.5 to +2.6
1
50
Com
Ind.
0 to +70
-40 to +85
–55 to +150
Unit
V
V
V
W
mA
°C
°C
°C
®
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DD MAX
V
DDQ MAX
V
IN
P
D MAX
I
CS
T
OPR
T
STG
Parameters
Maximum Supply Voltage
Maximum Supply Voltage for Output Buffer
Input Voltage
Allowable Power Dissipation
Output Shorted Current
Operating Temperature
Storage Temperature
DC RECOMMENDED OPERATING CONDITIONS
(2)
Commercial
(
T
A
= 0°C to +70°C), Industrial
(
T
A
= -40°C to +85°C)
Symbol
V
DD
, V
DDQ
V
IH
V
IL
Parameter
Supply Voltage
Input High Voltage
(3)
Input Low Voltage
(4)
Min.
1.7
0.8 x V
DDQ
-0.3
Typ.
1.8
—
—
Max.
1.9
V
DDQ
+ 0.3
+0.3
Unit
V
V
V
CAPACITANCE CHARACTERISTICS
(1,2)
(V
DD
= 1.8V, T
A
= +25°C, f = 1 MHz)
Symbol
C
IN
1
C
IN
2
CI/O
Parameter
Input Capacitance: CLK
Input Capacitance: (A0-A11, CKE,
CS, RAS, CAS, WE,
LDQM, UDQM)
Data Input/Output Capacitance: DQ0-DQ15
Min.
2.5
2.5
4.0
Max.
4.0
5.0
6.5
Unit
pF
pF
pF
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All voltages are referenced to Vss.
3. V
IH
(max) = 2.2V with a pulse width
≤
3 ns.
4. V
IL
(min) = -1.0V with a pulse width
≤
3 ns.
4
Integrated Silicon Solution, Inc. — www.issi.com —
Logic analyzers are widely used tools in digital design verification and debugging. They can verify the proper functioning of digital circuits and help users identify and troubleshoot faults. They ...[详细]
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