AS8506C
Battery Cell Monitor and Balancer IC
General Description
The AS8506C is a battery management IC dedicated to support
cell voltage measurement, monitoring, cell balancing and
temperature measurement functions in Li-Ion battery stacks for
industrial/consumer/PV battery applications.
Ambient temperature range is from -40°C to 85°C.
It features cell voltage diagnosis with externally adjustable
upper and lower cell voltage limits, fast cell voltage capture on
request through 12-bit SAR ADC, passive cell balancing by
simultaneous comparison of actual cell voltages with a
reference cell voltage and temperature measurement on two
external NTC sensors through 12-bit ADC.
Cells that are above reference will sequentially be discharged
through integrated switches and one external resistor.
There is also an active balancing option AS8506C-A through
factory setting to sequentially charge cells which are below
reference from an external DC-DC Flyback converter and an
integrated low side driver.
The device can be used flexibly for battery stacks up to 7 cells
with a minimum stack voltage of 6V and a maximum stack
voltage of 32V.
It can be chained to support battery packs of virtually any
number of cells in synchronized mode through chained clock
and trigger signal.
The status of the battery stack is communicated to outside
world through OR’d voltage_ok signal and balance ready signal.
Ordering Information
and
Content Guide
appear at end of
datasheet.
ams Datasheet (discontinued)
[v1-05] 2017-Jun-23
Page 1
Document Feedback
AS8506C −
General Description
Key Benefits & Features
The benefits and features of AS8506C, Battery Cell Monitor and
Balancer IC are listed below:
Figure 1:
Added Value of Using AS8506C
Benefits
•
Reduce filter / synchronization effort
•
Acquired data have same time stamp to
inherently generate accurate comparison results
independent from load transients
•
Strongly reduces data communication and data
processing and thereby improves EMC
robustness
•
To compensate accumulative charge differences
only. This mitigates cases of occasional wrong
balance decisions due to flat OCV characteristic
or mismatch in cell temperature
•
Intrinsic inter module balancing through charge
redistribution, efficiency improvement in case of
leakage path due to defect induced leakage in
particular cells
•
For OCV capture, cell impedance calculation,
diagnosis
•
Small form factor, low BOM
Features
•
Simultaneous cell voltage capture for safe operating
area (SOA) monitoring and balancing
•
Autonomous balancing and SOA monitoring
•
Autonomous passive balancing in the 100 mA range
•
Option for active charge balancing with very few
external components
•
Absolute cell voltage read out, read out of two
temperature sensors
•
40-pin MLF (6x6) package, very low number of
external components
Applications
The applications of AS8506C include:
•
The AS8506C is ideal for simultaneous cell monitoring and
cell balancing in stacked energy storage systems. Current
levels in the 100 mA range enables to compensate
accumulative SOC mismatch over the entire cell pack.
•
Typical applications are:
• Li-Ion batteries up to 200 cells
• Energy storage systems to buffer energy from PV
panels or for emergency power supplies
• Battery management for e-scooters and e-bikes
Page 2
Document Feedback
ams Datasheet (discontinued)
[v1-05] 2017-Jun-23
AS8506C −
General Description
Block Diagram
The functional blocks of this device are shown below:
Figure 2:
AS8506C Block Diagram
CVT_NOK_IN
WAKE_OUT
TRIG_OUT
CLK_OUT
VREF_H
VCELL7
Cnt7H
Cnt7L
EXT_RES_CTL
Balance and VREF_H
Switches Level Shifters
Cnt7
Cnt5
Cnt3
Cnt4
Cnt2
Cnt6
Cnt1
Level Shifters for Stack Communication / Status Signals
5V
Stack signals
V5V_IN
BD_IN
FD_IN
VSUP
VCELL6
Cnt6H
Cnt6L
Pre-regulator
High
Precision
Reference
LDO
V5V
REF_T
CELL_THU
CELL_THL
VREF_IN
TEMP_IN1
TEMP_IN2
VCELL5
Cnt5H
Cnt5L
AS8506C
VCELL7
comp7
Reference &
Threshold
Generation Circuit
C_out7
DAC
Over-temperature
Monitor
Temperature
Sensor /
Switch
Capacitor
Circuit
VCELL4
Cnt4H
Cnt4L
comp6
C_out6
Multiplexer & SAR Logic
DAC_IN[11:0]
VCELL6
VCELL5
comp5
VCELL[7:1]
Zero Cross
Detection Circuit
Stack
signals
C_out5
VCELL3
Cnt3H
Cnt3L
Level Shifters
VCELL4
comp4
C_out4
VCELL2
Cnt2H
Cnt2L
VCELL3
comp3
C_out3
CLK_IN
FSM,
Digital Registers,
OTP Logic
VCELL2
comp2
TRIG_IN
CS
SCLK
SDO
SDI
Cnt1H
Cnt1L
VCELL1
comp1
C_out1
C-GND
TSECH
TSECL
NC_T
GND
NC
RC Oscillator &
PWM Driver
VCELL1
C_out2
CVT_NOK_OUT
BD_OUT
MS_SL
ams Datasheet (discontinued)
[v1-05] 2017-Jun-23
WAKE_IN
FD_OUT
Page 3
Document Feedback
AS8506C −
Pin Assignment
Pin Assignment
Figure 3:
Pin Diagram of AS8506C
CVT_NOK_IN
TRIG_OUT
VREF_H
CLK_OUT
WAKE_OUT
32
MS_SL
BD_IN
40
39
38
VSUP
37
36
35
34
33
FD_IN
TSECH
TSECL
VCELL7
VCELL6
VCELL5
VCELL4
VCELL3
VCELL2
VCELL1
C-GND
31
V5V_IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
30
29
28
V5V
REF_T
TEMP_IN1
TEMP_IN2
CELL_THL
CELL_THU
CS
SCLK
SDI
SDO
AS8506C
MLF 6x6
27
26
25
24
GND
(Exposed pad)
23
22
21
WAKE_IN
BD_OUT
Page 4
Document Feedback
CVT_NOK_OUT
VREF_IN
FD_OUT
TRIG_IN
CLK_IN
NC_T
NC
GND
ams Datasheet (discontinued)
[v1-05] 2017-Jun-23
AS8506C −
Pin Assignment
Figure 4:
Pin Description
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin Name
TSECH
TSECL
VCELL7
VCELL6
VCELL5
VCELL4
VCELL3
VCELL2
VCELL1
C-GND
NC
VREF_IN
GND
Pin Type
Description
Flyback converter transformer secondary high side
Flyback converter transformer secondary low side
Battery cell 7 high level pin
Battery cell 6 high level pin
Analog input /
output
Battery cell 5 high level pin
Battery cell 4 high level pin
Battery cell 3 high level pin
Battery cell 2 high level pin
Battery cell 1 high level pin
Power supply
input
Battery cell 1 low level pin
Not connected
Analog input /
output
Power supply
input
Cell voltage reference value (cell target voltage of
battery)
Ground to the IC
This pin triggers the cell balancing in the device.
Short pulse is for receiving status and continuous
‘High’ for cell balancing. It also acts as a data line
during 3-wire communication.
Clock input pin in the Slave device. This pin also acts
as a clock during 3-wire communication. Scan clock
in scan mode.
This pin alerts when the cell voltage or the
device/cell temperature is not within limits. During
3-wire communication, the CRC error is indicated on
this pin. The internal device cell voltage or
temperature status is ORed with
CVT_NOK_IN
on
this pin.
14
TRIG_IN
Digital input
15
CLK_IN
16
CVT_NOK_OUT
Digital output
17
BD_OUT
The ‘device internal balance done’ and ‘balance done
from above device’ are ANDed on this pin. This pin in
Master device indicates the complete system
balance done. During address allocation process,
this pin will be ‘High’ if
BD_IN
is ‘High’.
Flyback converter gate/opto coupler drive (pad is
push-pull type) can drive up to 12mA.
18
FD_OUT
ams Datasheet (discontinued)
[v1-05] 2017-Jun-23
Page 5
Document Feedback
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
