74ABT125 — Quad Buffer with 3-STATE Outputs
January 2008
74ABT125
Quad Buffer with 3-STATE Outputs
Features
■
Non-inverting buffers
■
Output sink capability of 64mA, source capability of
■
■
■
■
General Description
The ABT125 contains four independent non-inverting
buffers with 3-STATE outputs.
32mA
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Nondestructive hot insertion capability
Disable time less than enable time to avoid bus
contention
Ordering Information
Order Number
74ABT125CSC
74ABT125CSJ
74ABT125CMTC
Package
Number
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Function Table
Inputs
A
n
L
L
H
Output
O
n
L
H
Z
L
H
X
B
n
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
HIGH Impedance
X
=
Immaterial
Pin Description
Pin Names
A
n
, B
n
O
n
Description
Inputs
Outputs
©1994 Fairchild Semiconductor Corporation
74ABT125 Rev. 1.4.0
www.fairchildsemi.com
74ABT125 — Quad Buffer with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
T
STG
T
A
T
J
V
CC
V
IN
I
IN
V
O
Storage Temperature
Parameter
Ambient Temperature Under Bias
Junction Temperature Under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage
(1)
Input Current
(1)
Voltage Applied to Any Output
Disabled or Power-Off State
HIGH State
Current Applied to Output in LOW State (Max.)
DC Latchup Source Current (Across Comm Operating Range)
Over Voltage Latchup (I/O)
Rating
–65°C to +150°C
–55°C to +125°C
–55°C to +150°C
–0.5V to +7.0V
–0.5V to +7.0V
–30mA to +5.0mA
–0.5V to 5.5V
–0.5V to V
CC
twice the rated I
OL
(mA)
–300mA
10V
Note:
1. Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
T
A
V
CC
∆
V /
∆
t
Supply Voltage
Minimum Input Edge Rate
Data Input
Enable Input
Parameter
Free Air Ambient Temperature
Rating
–40°C to +85°C
+4.5V to +5.5V
50mV/ns
20mV/ns
©1994 Fairchild Semiconductor Corporation
74ABT125 Rev. 1.4.0
www.fairchildsemi.com
2
74ABT125 — Quad Buffer with 3-STATE Outputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
IL
V
ID
I
OZH
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current Breakdown
Test
Input LOW Current
Input Leakage Test
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional
I
CC
/Input
Outputs Enabled
Outputs 3-STATE
Outputs 3-STATE
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
Min.
2.0
Typ.
Max. Units
V
0.8
–1.2
V
V
V
0.55
1
1
7
–1
–1
µA
µA
V
10
–10
–275
50
100
50
15
50
1.5
1.5
50
0.1
µA
µA
mA
µA
µA
µA
mA
µA
mA
mA
µA
mA/
MHz
V
µA
Min.
Min.
Min.
Max.
Max.
Max.
0.0
I
IN
=
–18mA
I
OH
=
–3mA
I
OH
=
–32mA
I
OL
=
64mA
V
IN
=
2.7V
(2)
V
IN
=
V
CC
V
IN
=
7.0V
V
IN
=
0.5V
(2)
V
IN
=
0.0V
I
ID
=
1.9µA, All Other Pins
Grounded
4.75
2.5
2.0
0–5.5V V
OUT
=
2.7V, OE
n
=
2.0V
0–5.5V V
OUT
=
0.5V, OE
n
=
2.0V
Max.
Max.
0.0
Max.
Max.
Max.
Max.
V
OUT
=
0.0V
V
OUT
=
V
CC
V
OUT
=
5.5V, All Others GND
All Outputs HIGH
All Outputs LOW
OE
n
=
V
CC
, All Others at V
CC
or Ground
V
I
=
V
CC
– 2.1V
Enable Input V
I
=
V
CC
– 2.1V
Data Input V
I
=
V
CC
– 2.1V,
All Others at V
CC
or Ground
Max.
Outputs OPEN, OE
n
=
GND
(3)
,
One-Bit Toggling,
50% Duty Cycle
I
CCD
Dynamic I
CC
No Load
(2)
Notes:
2. Guaranteed, but not tested.
3. For 8-bit toggling, I
CCD
<
0.8mA/MHz.
©1994 Fairchild Semiconductor Corporation
74ABT125 Rev. 1.4.0
www.fairchildsemi.com
3
74ABT125 — Quad Buffer with 3-STATE Outputs
AC Electrical Characteristics
T
A
=
+25°C,
V
CC
=
+5V,
C
L
=
50pF
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Output Enable Time
T
A
=
–40°C to +85°C
V
CC
=
4.5V–5.5V
C
L
=
50pF
Min.
1.0
1.0
1.0
1.0
1.0
1.0
Parameter
Propagation Delay, Data to Outputs
Min.
1.0
1.0
1.0
1.0
1.0
1.0
Typ.
Max.
4.6
4.9
5.1
6.8
6.2
5.5
Max.
4.6
4.9
5.1
6.8
6.2
5.5
Units
ns
ns
ns
Capacitance
Symbol
C
IN
C
OUT(4)
Parameter
Input Capacitance
Output Capacitance
V
CC
=
0V
Conditions
T
A
=
25°C
V
CC
=
5.0V
Typ.
5.0
9.0
Units
pF
pF
Note:
4. C
OUT
is measured at frequency f
=
1MHz, per MIL-STD-883, Method 3012.
©1994 Fairchild Semiconductor Corporation
74ABT125 Rev. 1.4.0
www.fairchildsemi.com
4
74ABT125 — Quad Buffer with 3-STATE Outputs
Physical Dimensions
8.75
8.50
7.62
14
8
B
A
0.65
5.60
6.00
4.00
3.80
PIN ONE
INDICATOR
1
7
1.70
1.27
1.27
(0.33)
0.51
0.35
0.25
M
LAND PATTERN RECOMMENDATION
C B A
1.75 MAX
1.50
1.25
0.25
0.10
C
0.10 C
SEE DETAIL A
0.25
0.19
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
X 45°
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
0.36
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.50
0.25
R0.10
R0.10
8°
0°
0.90
0.50
(1.04)
DETAIL A
SCALE: 20:1
SEATING PLANE
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1994 Fairchild Semiconductor Corporation
74ABT125 Rev. 1.4.0
www.fairchildsemi.com
5
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
