GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched
translator
Rev. 07 — 3 February 2009
Product data sheet
1. General description
The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a
GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-TTL sampling
receiver or as a TTL-to-GTL interface.
The GTL2005 LVTTL interface is tolerant up to 5.5 V allowing direct access to TTL or 5 V
CMOS outputs.
The GTL2005 V
ref
linearity degrades below 0.8 V (see
Section 10.1).
If the application
allows, use the GTL2014, otherwise more closely review noise margins.
fast t
PD
GTL2005
GTL2014
slow t
PD
GTL−
GTL
GTL+
002aab378
Fig 1.
GTL2005/GTL2014 positioning
2. Features
I
Operates as a quad GTL/GTL+ sampling receiver or as a LVTTL/TTL to GTL/GTL+
driver
I
Quad bidirectional bus interface
I
3.0 V to 3.6 V operation with 5 V tolerant LVTTL I/O
I
Live insertion/extraction permitted
I
Latch-up protection exceeds 500 mA per JESD78
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115, and 1000 V CDM per JESD22-CC101
I
Package offered: TSSOP14
NXP Semiconductors
GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
3. Quick reference data
Table 1.
Quick reference data
V
CC
= 3.3 V
±
0.3 V
Symbol
C
i
C
io
Parameter
input capacitance
input/output capacitance
Conditions
control inputs;
V
I
= 3.0 V or 0 V
A port;
V
O
= V
TT
or 0 V
B port;
V
O
= 3.0 V or 0 V
GTL; V
ref
= 0.8 V
t
PLH
t
PHL
t
PLH
t
PHL
[1]
All typical values are measured at V
CC
= 3.3 V and T
amb
= 25
°C.
Min
-
-
-
Typ
[1]
2.3
3.4
6.0
Max
3.5
5.0
7.0
Unit
pF
pF
pF
propagation delay, Bn to An see
Figure 7
propagation delay, An to Bn see
Figure 8
-
-
-
-
2.1
1.9
4.1
4.4
2.3
2.6
5.9
5.9
ns
ns
ns
ns
4. Ordering information
Table 2.
Ordering information
T
amb
=
−
40
°
C to +85
°
C
Type number
GTL2005PW
Topside
mark
GTL2005
Package
Name
TSSOP14
Description
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
Version
SOT402-1
GTL2005_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 3 February 2009
2 of 19
NXP Semiconductors
GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
5. Functional diagram
GTL2005
A0
B0
A1
B1
A2
B2
A3
B3
002aab151
VREF
DIR
Fig 2.
Logic diagram of GTL2005
6. Pinning information
6.1 Pinning
DIR
A0
A1
VREF
A2
A3
GND
1
2
3
4
5
6
7
002aab150
14 V
CC
13 B0
12 B1
GTL2005PW
11 GND
10 B2
9
8
B3
GND
Fig 3.
Pin configuration for TSSOP14
GTL2005_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 3 February 2009
3 of 19
NXP Semiconductors
GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
6.2 Pin description
Table 3.
Symbol
DIR
A0
A1
A2
A3
B0
B1
B2
B3
VREF
GND
V
CC
Pin description
Pin
1
2
3
5
6
13
12
10
9
4
7, 8, 11
14
GTL reference voltage
ground (0 V)
positive supply voltage
data inputs/outputs (B side, TTL)
Description
direction control input
data inputs/outputs (A side, GTL)
7. Functional description
Refer to
Figure 2 “Logic diagram of GTL2005”.
7.1 Function table
Table 4.
Function table
H = HIGH voltage level; L = LOW voltage level.
Input
DIR
H
L
Input/output
B (TTL)
inputs
An = Bn
A (GTL)
Bn = An
inputs
GTL2005_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 3 February 2009
4 of 19
NXP Semiconductors
GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
Parameter
DC supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
V
I
< 0 V
A port
B port
V
O
< 0 V
output in OFF or
HIGH state; A port
output in OFF or
HIGH state; B port
I
OL
I
OH
T
stg
[1]
Conditions
Min
−0.5
-
−0.5
[2]
−0.5
[2]
-
−0.5
[2]
−0.5
[2]
-
-
-
[3]
Max
+4.6
−50
+7.0
+4.6
−50
+7.0
+4.6
128
80
−64
+150
Unit
V
mA
V
V
mA
V
V
mA
mA
mA
°C
current into any output in
the LOW state
current into any output in
the HIGH state
storage temperature range
B port
A port
B port
−60
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under
Section 9 “Recommended operating conditions”
is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 150
°C.
[2]
[3]
GTL2005_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 3 February 2009
5 of 19
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