The SiP32448 and SiP32449 are low resistance slew rate
controlled load switches. The part operates from 1.7 V to
5.5 V supply and can tolerate negative voltage at input to
-2 V. The integrated charge pump drivers enable the part
with low on resistance over the wide input voltage range.
Both SiP32448 and SiP32449 feature a controlled soft-on
slew rate of typical 2.5 ms that limits the inrush current for
designs of heavy capacitive load and minimizes the resulting
voltage droop at the power rails.
The SiP32448 and SiP32449 feature a constant low voltage
control logic interface over the full operation voltage range.
It can interface with low voltage control signals without extra
level shifting circuit. When EN is left open, the part will not
turn on until V
IN
is greater than 2.5 V.
The SiP32449 has a output discharge to help discharge the
output capacitor during shutdown mode for fast turn off.
The SiP32448 and SiP32449 have exceptionally low
shutdown current and provides reverse blocking to prevent
high current flowing into the power source when the switch
is off or V
IN
is ground.
Both SiP32448 and SiP32449 are available in TDFN4
package of 1.2 mm x 1.6 mm x 0.55 mm.
FEATURES
• 1.7 V to 5.5 V input voltage range
• Negative input voltage tolerance down to -2 V
• 38 m typical R
ON
from 1.8 V to 5 V
• 3 A maximum continuous switch current
• Slew rate controlled turn-on: 2.5 ms at 3.6 V
• Constant low control logic: V
IH
= 1.15 V, V
IL
= 0.7 V
• 2 V UVLO when EN is open
• Reverse current blocking when switch is off or V
IN
is ground
• Output discharge (SiP32449)
• ESD protected
- HBM: >6 kV
- MM: >300 V
- IEC61000-4-2 air discharge: >15 kV
- IEC61000-4-2 contact discharge: >8 kV
• Compact TDFN4 package
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
Available
APPLICATIONS
• PDAs / smart phones
• Notebook / netbook computers
• Tablet PC
• Portable media players
• Digital camera
• GPS navigation devices
• Data storage devices
• Optical, industrial, medical, and healthcare devices
TYPICAL APPLICATION CIRCUIT
V
IN
IN
OUT
V
OUT
SiP32448, SiP32449
C
IN
2.2 µF
EN
EN
GND
C
OUT
1 µF
GND
GND
Fig. 1 -
SiP32448, SiP32449 Typical Application Circuit
S15-1920-Rev. C, 24-Aug-15
Document Number: 62959
1
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiP32448, SiP32449
www.vishay.com
Vishay Siliconix
ORDERING INFORMATION
Part Number
SiP32448DNP-T1-GE4
SiP32449DNP-T1-GE4
Package
TDFN4 1.2 mm x 1.6 mm
Marking
Lx
Px
Output Discharge
No
Yes
Temperature Range
-40 °C to +85 °C
Notes
•
x = Lot code
•
GE4 denotes halogen-free and RoHS compliant
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Input Voltage (V
IN
)
Enable Input Voltage (V
EN
)
Output Voltage (V
OUT
)
Maximum Continuous Switch Current (I
max.
)
c
Maximum Repetitive Pulsed Current (1 ms, 10 % Duty Cycle)
c
Maximum Non-Repetitive Pulsed Current (100 μs, EN = Active)
c
Junction Temperature (T
J
)
Thermal Resistance (q
JA
)
a
Power Dissipation (P
D
)
a,b
HBM
ESD Rating
MM
IEC41000-4-2 Air Discharge
d
IEC41000-4-2 Contact Discharge
d
Notes
a. Device mounted with all leads and power pad soldered or welded to PC board, see PCB layout.
b. Derate 5.9 mW/°C above T
A
= 25 °C, see PCB layout.
c. T
A
= 25 °C, see PCB layout.
d. Tested on V
IN
with 2.2 μF C
IN
. V
IN
connected to micro-USB connector.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
Limit
-2 to +6
-2 to +6
-0.3 to +6
4
7
12
-40 to +150
170
735
6
300
15
8
Unit
V
A
°C
°C/W
mW
kV
V
kV
RECOMMENDED OPERATING RANGE
Parameter
Input Voltage Range (V
IN
)
Operating Junction Temperature Range (T
J
)
Limit
1.7 to 5.5
-40 to +125
Unit
V
°C
S15-1920-Rev. C, 24-Aug-15
Document Number: 62959
2
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiP32448, SiP32449
www.vishay.com
Vishay Siliconix
Limits
-40 °C to +85 °C
Min.
1.7
V
IN
= -2 V
EN = open, 25 °C (switch On to Off)
EN = open, 25 °C (switch Off to On)
EN = open, 25 °C
V
IN
= 1.8 V, EN = active
V
IN
= 2.5 V, EN = active
-
-
2.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
IN
= 1.8 V to 5.5 V
V
EN
= 5.5 V
EN = inactive, T
A
= 25 °C (for SiP32449 only)
V
IN
= 3.6 V, R
load
= 10
,
T
A
= 25 °C
-
1.15
d
-6
-
-
1
a
SPECIFICATIONS
Parameter
Operating Voltage
c
Negative Input Voltage Tolerance
Under Voltage Lock Out
UVLO Hysteresis
Symbol
V
IN
I
NEG
UVLO
H-L
UVLO
L-H
UVLO
HYS
Test Conditions Unless Specified
V
IN
= 5 V, T
A
= -40 °C to +85 °C
(Typical values are at T
A
= 25 °C)
Unit
a
Typ.
-
-15
-
-
b
Max.
5.5
-
2
-
-
50
90
110
130
180
18
1
10
43
43
43
43
43
-
0.7
d
-
6
280
-
3.8
V
mA
V
0.25
35
54
78
93
110
8
-
-
38
38
38
38
38
3100
-
-
-
210
1.35
1.7
-
Quiescent Current
I
Q
V
IN
= 3.6 V, EN = active
V
IN
= 4.3 V, EN = active
V
IN
= 5 V, EN = active
μA
Off Supply Current
Off Switch Current
Reverse Blocking Current
I
Q(off)
I
DS(off)
I
RB
EN = inactive, OUT = open
EN = inactive, OUT = GND
V
OUT
= 5 V, V
IN
= 0 V, V
EN
= inactive
V
IN
= 1.8 V, I
L
= 500 mA, T
A
= 25 °C
V
IN
= 2.5 V, I
L
= 500 mA, T
A
= 25 °C
On-Resistance
R
DS(on)
V
IN
= 3.6 V, I
L
= 500 mA, T
A
= 25 °C
V
IN
= 4.3 V, I
L
= 500 mA, T
A
= 25 °C
V
IN
= 5 V, I
L
= 500 mA, T
A
= 25 °C
m
On-Resistance Temp.-Coefficient
EN Input Low Voltage
c
EN Input High Voltage
c
EN Input Leakage
Output Pulldown Resistance
Output Turn-On Delay Time
Output Turn-On Rise Time
TC
RDS
V
IL
V
IH
I
SINK
R
PD
t
d(on)
t
(on)
ppm/°C
V
μA
ms
t
d(off)
-
Output Turn-Off Delay Time
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. For V
IN
outside this range consult typical EN threshold curve.
d. Not tested, guarantee by design.
0.005
PIN CONFIGURATION
OUT
4
GND
EN
3
2
GND
1
IN
Bottom View
Fig. 2 - TDFN4 1.2 mm x 1.6 mm Package
PIN DESCRIPTION
Pin Number
1
2
3
4
Name
IN
GND
EN
OUT
Function
This is the input pin of the switch
Ground connection
Enable input
This is the output pin of the switch
S15-1920-Rev. C, 24-Aug-15
Document Number: 62959
3
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiP32448, SiP32449
www.vishay.com
BLOCK DIAGRAM
V
IN
Vishay Siliconix
Negative
Voltage
Detect / Clamp
EN
Control
Logic
Charge
Pump
Turn-on
Slew Rate
Control
Output
Discharge
SiP32449 only
GND
SiP32448, SiP32449
Fig. 3 - Functional Block Diagram
DETAILED DESCRIPTION
SiP32448 and SiP32449 are advanced slew rate controlled
high side load switches with an integrated N-channel power
switch. When the device is enabled the gate of the power
switch is turned on at a controlled rate to avoid excessive
inrush current. Once fully on the gate to source voltage of
the power switch is biased at a constant level. The design
gives a flat on resistance throughout the operating voltages.
A special reverse blocking circuitry prevents current flowing
from output to input when the switch is off. The V
IN
and EN
pin can tolerate -2 V voltage without drawing excessive
current.
control logic threshold over the operation voltage range.
When enable pin is left open, a built-in voltage divider sets
the internal logic. The switch will turn on when the V
IN
exceeds the UVLO trip point.
Reverse Voltage Protection
The SiP32448 and SiP32449 contain a reverse blocking
circuitry to protect the current from going to the input from
the output when the switch is off. Reverse blocking works
for input voltage as low as 0 V.
In case the EN pin is left open, the reverse blocking circuitry
will prevents current flow from output pin to input pin if the
output voltage is higher by at least 1 V than the input
voltage.
APPLICATION INFORMATION
Input Capacitor
In general, under steady state conditions the SiP32448 and
SiP32449 do not require an input capacitor. Nevertheless,
an input bypass capacitor is recommended in order to
reduce the input voltage drop caused by transient inrush
currents. Commonly, a 2.2 μF ceramic capacitor is sufficient
and should be placed in close proximity to V
IN
and GND
pins. A higher value input capacitor can help to further
reduce the voltage drop. Ceramic capacitors are
recommended for their low ESR characteristic.
Output Capacitor
While these devices work without an output capacitor, a
1 μF or higher value capacitor across V
OUT
and GND is
recommended in order to handle potential load transient
conditions. In the event that the switch is turning of while
running high current, circuit stray inductances might force
the output to some negative voltage in order to mitigate this
phenomenon a proper output capacitor is required.
Enable
The device is logic high active. Enable pin voltage can
exceed V
IN
as long as it is within the absolute maximum
rating range. The EN pin is compatible with both TTL and
CMOS logic voltage levels. The part features a constant
S15-1920-Rev. C, 24-Aug-15
THERMAL CONSIDERATIONS
The maximum allowed DC Current depends on the thermal
condition in which the device operates. In order to calculate
max allowed DC current, first the max power dissipation
should be considered.
The SiP32448 and SiP32449 are packaged in a TDFN4
1.2 mm x 1.6 mm package which has a thermal resistance of
J-Aa
= 170 °C/W.
Note
a. Device mounted with all leads and power pad soldered or
welded to PC board, see PCB layout. For any other layout
configuration the actual junction to ambient thermal impedance
should be considered
The following formula shows the maximum allowed power
dissipation as a function of the ambient temperature T
A
when the maximum junction temperature is limited to
T
J (max.)
= 125 °C:
P
max.
=
T
J (max.)
- T
A
θ
J-A
=
125
- T
A
170
For example at ambient temperature of 70 °C, the maximum
power dissipation will be limited to about 324 mW.
Document Number: 62959
4
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiP32448, SiP32449
www.vishay.com
In order to calculate the maximum allowed DC current the
switch R
DS(on)
temperature dependency should be
considered.
As an example let us calculate maximum load current
at T
A
= 70 °C and input voltage of 1.8 V. At this input voltage
the R
DS(on)
at 25 °C 43 m (see specification table). The
R
DS(on)
at 125 °C can be extrapolated from this data using
the following formula:
Negative Input Voltage
The SiP32448 and SiP32449 can withstand maximum
negative 2 V at its input due to any spike from abnormal or
fault condition of the system.
Recommended Board Layout
For improved performance, all traces should be as short as
possible to minimize stray inductances and parasitic effects.
The input and output capacitors should be kept as close
as possible to the input and output pins respectively.
Connecting the central exposed pad to GND, using wide
traces for input, output, and GND help reducing the case to
ambient thermal impedance. See fig. 4.
Vishay Siliconix
R
DS(on)_125 °C
= R
DS(on)_25 °C
x (1 + T
C
x (T
J max.
- 25)/100 )
Where T
C
is the R
DS(on)
temperature coefficient expressed in
percent change per degree C.
For SiP32448 the approximated value is 0.31 %/°C. T
J max.
is the maximum allowed junction temperature (125 °C).
Therefore,
BOARD LAYOUT
R
DS(on) (at 125 °C)
=
43 mΩ x (1 + 0.31 x (125 - 25)/100 ) ≈ 57 mΩ
The maximum current limit is then determined by
P (max.)
R
DS
(
on
)
I
LOAD
(max.)
<
Which in this case is 2.38 A.
Due to device limitation the max switch DC current
should exceed 3 A in any condition.
To obtain the highest power dissipation the power pad of
the device should be connected to a heat sink on the printed
circuit board. Figure 4 shows a typical PCB layout. All
copper traces and vias for the V
IN
and V
OUT
pins should be
sized adequately to carry the maximum continuous current.
Fig. 4 -
Recommended Board Layout
TYPICAL APPLICATION SCHEMATIC
Fig. 5 -
Application Schematic
S15-1920-Rev. C, 24-Aug-15
Document Number: 62959
5
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
1. Introduction
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