Freescale Semiconductor
Technical Data
Document Number: MC13202
Rev. 1.5, 12/2008
MC13202
MC13202
2.4 GHz Low Power Transceiver
for the IEEE
®
802.15.4 Standard
Device
Package Information
Plastic Package
Case 1311-03
Ordering Information
Device Marking
13202
13202
Package
QFN-32
QFN-32
MC13202FC
MC13202FCR2
(Tape and Reel)
1
Introduction
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 4
Data Transfer Modes . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . 8
Functional Description . . . . . . . . . . . . . . . . 12
Pin Connections . . . . . . . . . . . . . . . . . . . . . . 15
Crystal Oscillator Reference Frequency . . 19
Transceiver RF Configurations
and External Connections
22
10Packaging Information . . . . . . . . . . . . . . . . 28
1
2
3
4
5
6
7
8
9
The MC13202 is a short range, low power, 2.4 GHz
Industrial, Scientific, and Medical (ISM) band
transceivers. The MC13202 contains a complete
802.15.4 physical layer (PHY) modem designed for the
IEEE
®
802.15.4 Standard which supports peer-to-peer,
star, and mesh networking.
The MC13202 includes the 802.15.4 PHY/MAC for use
with the HCS08 Family of MCUs. The MC13202 can be
used with Freescale’s IEEE 802.15.4 MAC and
BeeStack, which is Freescale’s ZigBee
®
compliant
protocol stack.
When combined with an appropriate microcontroller
(MCU), the MC13202 provides a cost-effective solution
for short-range data links and networks. Interface with
the MCU is accomplished using a four wire serial
peripheral interface (SPI) connection and an interrupt
request output which allows for the use of a variety of
processors. The software and processor can be scaled to
fit applications ranging from simple point-to-point
systems, through complete ZigBee networking. For
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
© Freescale Semiconductor, Inc., 2005, 2006, 2007, 2008. All rights reserved.
more detailed information about MC13202 operation, refer to the
MC13202 Reference Manual,
(MC13202RM).
Applications include, but are not limited to, the following:
• Residential and commercial automation
— Lighting control
— Security
— Access control
— Heating, ventilation, air-conditioning (HVAC)
— Automated meter reading (AMR)
• Industrial Control
— Asset tracking and monitoring
— Homeland security
— Process management
— Environmental monitoring and control
— HVAC
— Automated meter reading
• Health Care
— Patient monitoring
— Fitness monitoring
• Consumer
— Human interface devices (keyboard, mice, etc.)
— Remote control
— Wireless toys
The transceiver includes a low noise amplifier, 1.0 mW power amplifiers (PA), onboard RF
transmit/receive (T/R) switch for single port use, PLL with internal voltage controlled oscillator (VCO),
on-board power supply regulation, and full spread-spectrum encoding and decoding. The device supports
250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with 5.0 MHz
channel spacing per the 802.15.4 Standard. The SPI port and interrupt request output are used for receive
(RX) and transmit (TX) data transfer and control.
2
•
•
•
•
•
Features
Recommended power supply range: 2.0 to 3.4 V
Fully compliant 802.15.4 Standard transceiver supports 250 kbps O-QPSK data in 5.0 MHz
channels and full spread-spectrum encode and decode
Operates on one of 16 selectable channels in the 2.4 GHz band
-1 to 0 dBm nominal output power, programmable from -27 dBm to +3 dBm typical
Receive sensitivity of <-92 dBm (typical) at 1% PER, 20-byte packet, much better than the
802.15.4 Standard of -85 dBm
MC13202 Technical Data, Rev. 1.5
2
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
•
Integrated transmit/receive switch
Dual PA output pairs which can be programmed for full differential single port or dual port
operation that supports an external LNA and/or PA
Three power down modes for increased battery life
— < 1 µA Off current
— 1.0 µA Typical Hibernate current
— 35 µA Typical Doze current (no CLKO)
Programmable frequency clock output (CLKO) for use by MCU
Onboard trim capability for 16 MHz crystal reference oscillator eliminates need for external
variable capacitors and allows for automated production frequency calibration
Four internal timer comparators available to supplement MCU timer resources
Supports both Packet Mode and Streaming Mode data transfer
Buffered transmit and receive data packets for simplified use with low cost MCUs
Seven GPIO to supplement MCU GPIO
Operating temperature range: -40 °C to 85 °C
Small form factor QFN-32 Package
— Meets moisture sensitivity level (MSL) 3
— 260 °C peak reflow temperature
— Meets lead-free requirements
2.1
Software Features
Freescale provides a wide range of software functionality to complement the MC13202 hardware. There
are three levels of application solutions:
1. Simple proprietary wireless connectivity.
2. User networks built on the 802.15.4 MAC standard.
3. ZigBee-compliant network stack.
2.1.1
•
•
•
•
Simple MAC (SMAC)
Small memory footprint (about 3 Kbytes typical)
Supports point-to-point and star network configurations
Proprietary networks
Source code and application examples provided
MC13202 Technical Data, Rev. 1.5
Freescale Semiconductor
3
2.1.2
•
•
•
•
802.15.4 Standard-Compliant MAC
Supports star, mesh and cluster tree topologies
Supports beaconed networks
Supports GTS for low latency
Multiple power saving modes (idle doze, hibernate)
2.1.3
•
•
•
ZigBee-Compliant Network Stack
Supports all ZigBee specifications
Supports star, mesh and tree networks
Advanced Encryption Standard (AES) 128-bit security
3
Block Diagrams
Figure 1
shows a simplified block diagram of the MC13202 which is an 802.15.4 Standard compatible
transceiver that provides the functions required in the physical layer (PHY) specification.
Symbol
Synch & Det
Correlator
1st IF Mix er
LNA IF = 65 MHz
2nd IF Mix er
IF = 1 MHz PMA
Decimation Baseband Matched
Filter
Mix er
Filter
Packet
Processor
Analog
Regulator
Pow er-Up
Control
Logic
Digital
Regulator L
Digital
Regulator H
Cry stal
Regulator
VDDA
VBATT
VDDINT
VDDD
CCA
DCD
RFIN_P
(PAO_P)
RFIN_M
(PAO_M)
T/ R
AGC
Receiv e
Packet RAM
Receiv e RAM
Arbiter
Sequence
Manager
(Control Logic)
VCO
Regulator
VDDVCO
CT_Bias
VDDLO2
256 MHz
RXTXEN
÷
4
Programmable
Prescaler
24 Bit Ev ent Timer
XTAL1
XTAL2
Crystal
Oscillator
16 MHz
SERIAL
PERIPHERAL
INTERFACE
(SPI)
4 Programmable
Timer Comparators
CE
MOSI
MISO
SPICLK
ATTN
RST
Synthesizer
Transmit
Packet RAM 2
Transmit
Packet RAM 1
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
Transmit RAM
Arbiter
Sy mbol
Generation
IRQ
Arbiter
IRQ
VDDLO1
2.45 GHz
VCO
PAO_P
PAO_M
PA
Phase Shift Modulator
MUX
CLKO
FCS
Generation
Header
Generation
Figure 1. 802.15.4 Modem Simplified Block Diagram
MC13202 Technical Data, Rev. 1.5
4
Freescale Semiconductor
Figure 2
shows the basic system block diagram for the MC13202 in an application. Interface with the
transceiver is accomplished through a 4-wire SPI port and interrupt request line. The media access control
(MAC), drivers, and network and application software (as required) reside on the host processor. The host
can vary from a simple 8-bit device up to a sophisticated 32-bit processor depending on application
requirements.
MC13202
Analog Receiver
Digital Transceiver
Control
Logic
SPI
and GPIO
Microcontroller
SPI
Timer
A/D
ROM
(Flash)
RAM
RAM Arbiter
IRQ Arbiter
Timer
CPU
Application
Network
Voltage
Regulators
Power Up
Management
Buffer RAM
MAC
PHY Driver
Frequency
Generation
Analog
Transmitter
Figure 2. System Level Block Diagram
4
Data Transfer Modes
The MC13202 has two data transfer modes:
1. Packet Mode — Data is buffered in on-chip RAM
2. Streaming Mode — Data is processed word-by-word
The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer. For proprietary
applications, packet mode can be used to conserve MCU resources.
4.1
Packet Structure
Figure 3
shows the packet structure of the MC13202. Payloads of up to 125 bytes are supported. The
MC13202 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a one-byte Frame
Length Indicator (FLI) before the data. A Frame Check Sequence (FCS) is calculated and appended to the
end of the data.
4 bytes
Preamble
1 byte
SFD
1 byte
FLI
125 bytes maximum
Payload Data
2 bytes
FCS
Figure 3. MC13202 Packet Structure
MC13202 Technical Data, Rev. 1.5
Freescale Semiconductor
5
DSP 与 ARM 处理器
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