®
ISL88550A
Data Sheet
April 23, 2008
FN6168.3
Synchronous Step-Down Controller with
Sourcing and Sinking LDO Regulator
ISL88550A integrates a synchronous buck PWM controller
to generate VDDQ, a sourcing and sinking LDO linear
regulator to generate VTT, and a 10mA reference output
buffer to generate VTTR. The buck controller drives two
external N-Channel MOSFETs to generate output voltages
down to 0.7V from a 2V to 25V input with output currents up
to 15A. The LDO can source up to 2.5A and sink up to -2.0A
continuously. Both the LDO output and the 10mA reference
buffer output can be made to track the REFIN voltage via a
built-in resistive divider. These features make the
ISL88550A ideally suited for DDR memory applications in
desktops, notebooks and graphics cards.
The PWM controller in the ISL88550A uses constant-on-time
PWM architecture with a programmable switching frequency
of up to 600kHz. This control scheme handles wide
input/output voltage ratios with ease and provides 100ns
“instant-on” response to load transients while maintaining
high efficiency and a relatively constant switching frequency.
The ISL88550A offers full programmable UVP/OVP and skip
mode options ideal in portable applications. Skip mode
allows for improved efficiency at lighter loads.
The VTT and VTTR outputs track to VREFIN/2. The high
bandwidth of this LDO regulator allows excellent transient
response without the need for bulk capacitors, thus reducing
the cost and size.
The buck controller and LDO regulators are provided with
independent current limits. Adjustable loss-less fold-back
current limit for the buck regulator is achieved by monitoring
the drain-to-source voltage drop of the low side synchronous
MOSFET. Once overcurrent is removed, the regulator is
allowed to enter soft-start again. This helps minimize power
dissipation during short-circuit condition. Additionally,
overvoltage and undervoltage protection mechanisms are
built in. The ISL88550A allow flexible sequencing and
standby power management using SHDNA#, and STBY#
inputs.
Features
• Pb-Free (RoHS Compliant)
Buck Controller
• Constant-On PWM with 100ns Load-Step Response
• Start-up with Pre-biased Output Voltage
• Up to 95% Efficiency
• 2V to 25V Input Voltage Range
• 2.5V Fixed or 0.7V to 3.5V Adjustable Output
• 200kHz/300kHz/450kHz/600kHz Switching Frequencies
• Programmable Current Limit with Foldback Capability
• 1.7ms Digital Soft-Start and Independent Shutdown
• Overvoltage/Undervoltage Protection Option
• Power-Good Window Comparator
LDO Section
• Fully Integrated VTT and VTTR Capability
• VTT has +2.5A/-2.0A Sourcing/Sinking Capability
• Start-Up with Pre-Biased Output Voltage
• VTT and VTTR Outputs Track VREFIN/2
• VTT and VTTR 1% of VREFIN/2
• Low All-Ceramic Output Capacitor Designs
• 1.0V to 2.8V Input REFIN Range
• Analog Soft-Start Option and Independent Shutdown
• Power-Good Window Comparator
Applications
• DDR, DDR II and DDR III Memory Power Supplies
• Desktop Computers
• Notebooks and Desknotes
• Graphics Cards
• Game Consoles
• Networking and RAID
Ordering Information
PART NUMBER (Note)
ISL88550AIRZ
ISL88550AIRZ-T*
PART MARKING
ISL88 550AIRZ
ISL88 550AIRZ
TEMP RANGE (°C)
-40 to +85
-40 to +85
PACKAGE (Pb-free)
28 Ld 5×5 TQFN
28 Ld 5×5 TQFN Tape and Reel
PKG. DWG. #
L28.5x5B
L28.5x5B
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2007, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL88550A
Pinout
ISL88550A
(28 LD TQFN)
TOP VIEW
SHDNA#
PGND1
23
SKIP#
AVDD
GND
VDD
22
21
20
19
18
17
16
15
8
SS
9
VTTS
10
VTTR
11
PGND2
12
VTT
13
VTTI
14
REFIN
LGATE
BOOT
PHASE
UGATE
VIN
OUT
FB
TP0
28
TON
OVP/UVP
REF
ILIM
POK1
POK2
STBY#
1
2
3
4
5
6
7
27
26
25
24
2
FN6168.3
April 23, 2008
ISL88550A
Absolute Maximum Ratings
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +25V
VDD, AVDD, VTTI to GND. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
SHDNA#, REFIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
SS, POK1, POK2, SKIP#, ILIM, FB to GND . . . . . . . . . . -0.3V to 6V
STBY#, TON, REF, UVP/OVP to GND . . . . . . -0.3V to AV
DD
+ 0.3V
OUT, VTTR to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to AV
DD
+ 0.3V
LGATE to PGND1 . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+ 0.3V
UGATE to PHASE . . . . . . . . . . . . . . . . . . . . -0.3V to VBOOT + 0.3V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
VTT to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VTTI + 0.3V
VTTS to GND. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to AV
DD
+ 0.3V
PGND1, PGND2 to GND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
REF Short Circuit to GND. . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Thermal Information
Thermal Resistance
28 Ld TQFN Package (Notes 1, 2). . . .
θ
JA
(°C/W)
32
θ
JC
(°C/W)
2.5
Operating Conditions
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . -65°C + 150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For
θ
JC
, the "case temp" location is the center of the exposed metal pad on the package underside.
3. Following are target specifications. Final limits may change as a result of characterization.
Electrical Specifications
V
IN
= +15V, V
DD
= AV
DD
= SHDNA# = STBY# = BOOT = ILIM = 5V, OUT = REFIN = VTTI = 2.5V,
FB = SKIP# = OVP/UVP = GND. PGND1 = PGND2 = PHASE = GND, VTTS = VTT, t
ON
= OPEN, T
A
= -40°C to
+85°C, Unless otherwise specified, parts are 100% tested at +25°C. Temperature limits established by
characterization and are not production tested. (Note 4).
CONDITIONS
MIN
TYP
MAX
UNIT
PARAMETER
MAIN PWM CONTROLLER
V
IN
Input Voltage Range
V
DD
, AV
DD
Input Voltage Range
Output Adjust Range
Output Voltage Accuracy (Note 5)
FB = OUT
FB = GND
Soft-Start Ramp Time
ON-Time
2
4.5
0.7
0.693
2.470
0.7
2.5
1.7
170
213
316
461
200
194
243
352
516
300
25
SHDNA# = STBY# = GND
All on (PWM, VTT, and VTTR on), V
FB
= 0.75V
STBY# = GND (only VTTR and PWM on),
V
FB
= 0.75V
SHDNA# = STBY# = GND
Rising edge of AV
DD
Hysteresis
4.1
1
2.5
1
2
4.25
50
25
5.5
3.5
0.707
2.53
V
V
V
V
V
ms
Rising edge of SHDNA# to full current limit
V
IN
= 15V,
V
OUT
= 1.5V
(Note 6)
t
ON
= GND (600kHz)
t
ON
= REF (450kHz)
t
ON
= OPEN (300kHz)
t
ON
= AV
DD
(200kHz)
219
273
389
571
450
40
5
5
2
10
4.4
ns
ns
ns
ns
ns
µA
µA
mA
mA
µA
V
mV
Minimum, OFF-Time
V
IN
Quiescent Supply Current
V
IN
Shutdown Supply Current
Combined AV
DD
and V
DD
Quiescent Supply
Current
(Note 6)
Combined AV
DD
and V
DD
Shutdown Supply
Current
AV
DD
Undervoltage Lockout Threshold
REFERENCE
Reference Voltage
Reference Load Regulation
AV
DD
= 4.5V to 5.5V; I
REF
= 0µA to 130µA
I
REF
= 0µA to 50µA
1.98
2
2.02
0.01
V
V
3
FN6168.3
April 23, 2008
ISL88550A
Electrical Specifications
V
IN
= +15V, V
DD
= AV
DD
= SHDNA# = STBY# = BOOT = ILIM = 5V, OUT = REFIN = VTTI = 2.5V,
FB = SKIP# = OVP/UVP = GND. PGND1 = PGND2 = PHASE = GND, VTTS = VTT, t
ON
= OPEN, T
A
= -40°C to
+85°C, Unless otherwise specified, parts are 100% tested at +25°C. Temperature limits established by
characterization and are not production tested. (Note 4).
(Continued)
CONDITIONS
V
REF
rising
Hysteresis
FAULT DETECTION
OVP Trip Threshold (Referenced to Nominal
V
OUT
)
UVP Trip Level Referred to Nominal V
OUT
POK1 Trip Level Referred to Nominal V
OUT
POK2 Trip Level Referred to Nominal VTTS
and VTTR
POK2 Disable Threshold (Measured at
REFIN)
UVP Blanking Time
OVP, UVP, POK_ Propagation Delay
POK_ Output Low Voltage
POK_ Leakage Current
ILIM Adjustment Range
ILIM Input Leakage Current
Current Limit Threshold (Fixed)
PGND1 to PHASE
Current Limit Threshold (Adjustable)
PGND1 to PHASE
Current-Limit Threshold (Negative Direction)
PGND1 to PHASE
Current-Limit Threshold (Negative Direction)
PGND1 to PHASE
Current-Limit Threshold (Zero Crossing)
PGND1 to PHASE
Thermal Shutdown Threshold
Rising
Hysteresis
INTERNAL BOOT DIODE
V
D
Forward Voltage
I
BOOT_LEAKAGE
Leakage Current
MOSFET DRIVERS
UGATE Gate Driver ON-Resistance
LGATE Gate Driver ON-Resistance in High
State
LGATE Gate Driver ON-Resistance in Low
State
Dead Time (Additional to Adaptive Delay)
LGATE rising
UGATE rising
INPUTS AND OUTPUTS
Logic Input Threshold High (SHDNA#, SKIP#, Rising edge
STBY#)
Hysteresis
Logic Input Current (SHDNA#, SKIP#, STBY#)
FB Input Logic Level
Low (2.5V output)
1.2
1.7
225
-1
1
0.1
2.20
V
mV
µA
V
V
BOOT
- V
PHASE
= 5V
1.5
1.5
0.6
30
30
5
5
3
Ω
Ω
Ω
ns
ns
PVCC - V
BOOT
, I
F
= 10mA
V
BOOT
= 25V, PHASE = 20V, PVCC = 5V
0.60
300
0.70
500
V
nA
ILIM = AV
DD
V
ILIM
= 2V
SKIP# = AV
DD
SKIP# = AV
DD,
ILIM = 2V
45
170
-75
50
200
-60
-250
3
150
15
I
SINK
= 4mA
V
POK_
= 5.5V, VFB = 0.8V, VTTS = 1.3V
0.25
Lower level, falling edge, 1% hysteresis
Upper level, rising edge, 1% hysteresis
Lower level, falling edge, 1% hysteresis
Upper level, rising edge, 1% hysteresis
V
REFIN
rising (Hysteresis = 75mV typical)
From rising edge of SHDNA#
UVP/OVP = AV
DD
110
65
87
107
87.5
107.5
0.7
8
14
10
0.3
1
2.00
0.1
55
235
-45
114
70
90
110
90
110
118
75
93
113
92.5
112.5
0.9
25
%
%
%
%
%
%
V
ms
µs
V
µA
V
µA
mV
mV
mV
mV
mV
°C
°C
MIN
TYP
1.93
300
MAX
UNIT
V
mV
PARAMETER
REF Undervoltage Lockout
4
FN6168.3
April 23, 2008
ISL88550A
Electrical Specifications
V
IN
= +15V, V
DD
= AV
DD
= SHDNA# = STBY# = BOOT = ILIM = 5V, OUT = REFIN = VTTI = 2.5V,
FB = SKIP# = OVP/UVP = GND. PGND1 = PGND2 = PHASE = GND, VTTS = VTT, t
ON
= OPEN, T
A
= -40°C to
+85°C, Unless otherwise specified, parts are 100% tested at +25°C. Temperature limits established by
characterization and are not production tested. (Note 4).
(Continued)
CONDITIONS
MIN
-0.1
High
Floating
REF
Low
Logic Input Current (t
ON
, OVP/UVP, Note 5)
OUT Input Resistance
FB = GND
FB Adjustable Mode
OUT Discharge Mode ON-Resistance
LINEAR REGULATORS (VTTR AND VTT)
VTTI Input Voltage Range
VTTI Supply Current
VTTI Shutdown Current
REFIN Input Impedance
REFIN Range
VTT, VTTR UVLO Threshold (Measured at
OUT)
Soft-Start Charge Current
VTT internal MOSFET High-Side
ON-Resistance
VTT internal MOSFET Low-Side
ON-Resistance
VTT Output Accuracy (Referenced to VTTR)
VTT Load Regulation
V
SS
= 0
I
VTT
= -100mA, V
VTTI
= 1.5V, AV
DD
= 4.5V
(T
J
= +125°C)
I
VTT
= 100mA, AV
DD
= 4.5V (T
J
= +125°C)
V
REFIN
= 1.8V or 2.5V, I
VTT
= ±5mA
V
REFIN
= 2.5V, I
VTT
= 0A to ±1.5A
V
REFIN
= 1.8V, I
VTT
= 0A to ±1.5A
VTT Positive Current Limit
VTT Negative Current Limit
VTTS Input Current
VTT = 0
VTT = VTTI
V
VTTS
= 1.5V, VTT Open
-1.25
±20
±40
2.5
-3.5
-1.5
1
1
3.0
-2.5
0.1
4.0
-2.0
1
1.25
±60
I
VTT
= I
VTTR
= 0
SHDNA# = STBY# = GND
V
REFIN
= 2.5V
17
1.0
0.01
0.1
4
0.10
0.18
0.28
0.43
1.5
20
1.0
0.1
2.8
1
10
27
2.8
0.2
V
mA
µA
kΩ
V
V
µA
Ω
Ω
%
%
%
A
A
µA
%
mA
-3
125
125
250
250
15
AV
DD
- 0.4
3.15
1.65
3.85
2.35
0.5
+3
500
500
30
TYP
MAX
0.1
UNIT
µA
V
V
V
V
µA
kΩ
kΩ
Ω
PARAMETER
Input Bias Current (FB)
Four-Level Input Logic Levels
(t
ON
, OVP/UVP)
VTTR Output Error (Referenced to V
REFIN
/2) V
REFIN
= 1.8V, I
VTTR
= 0mA
VTTR Current Limit
NOTES:
4. Limits established by characterization and are not production tested.
VTTR = 0 or VTTI
5. When the inductor is in continuous conduction, the output voltage will have a DC regulation level higher than the error comparator threshold by
50% of the ripple. In discontinuous conduction, the output voltage will have a DC regulation level higher than the trip level by approximately 1.5%
due to slope compensation.
6. On-time and off-time specifications are measured from 50% point to 50% point at the UGATE pin with PHASE = GND, V
BOOT
= 5V, and a 250pF
capacitor connected from UGATE to PHASE. Actual in-circuit times may differ due to MOSFET switching speeds.
5
FN6168.3
April 23, 2008
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