MC74HC4040A
12-Stage Binary Ripple
Counter
High−Performance Silicon−Gate CMOS
The MC74C4040A is identical in pinout to the standard CMOS
MC14040. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of 12 master−slave flip−flops. The output of
each flip−flop feeds the next and the frequency at each output is half of
that of the preceding one. The state counter advances on the
negative−going edge of the Clock input. Reset is asynchronous and
active−high.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with the Clock of the
HC4040A for some designs.
Features
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
V
CC
16
Q11
15
Q10
14
Q8
13
Q9
12
Reset Clock
11
10
Q1
9
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With JEDEC Standard No. 7A Requirements
Chip Complexity: 398 FETs or 99.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free and are RoHS Compliant
9
7
6
5
Clock
10
3
2
4
13
12
14
15
1
Reset
11
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
1
Q12
2
Q6
3
Q5
4
Q7
5
Q4
6
Q3
7
Q2
8
GND
16−Lead Package
(Top View)
MARKING DIAGRAMS
16
HC4040AG
AWLYWW
1
SOIC−16
A
L, WL
Y, YY
W, WW
G or
G
1
TSSOP−16
16
HC40
40A
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Clock
Reset
L
L
H
Output State
No Charge
Advance to Next State
All Outputs Are Low
X
Pin 16 = V
CC
Pin 8 = GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Figure 1. Logic Diagram
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 9
Publication Order Number:
MC74HC4040A/D
MC74HC4040A
MAXIMUM RATINGS
Symbol
V
CC
V
in
V
out
I
in
I
out
I
CC
P
D
T
stg
T
L
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
SOIC Package†
TSSOP Package†
Value
–0.5 to +7.0
–0.5 to V
CC
+ 0.5
–0.5 to V
CC
+ 0.5
±20
±25
±50
500
450
–65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
_C
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature Range, All Package Types
Input Rise and Fall Time
(Figure 2)
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Min
2.0
0
–55
0
0
0
0
Max
6.0
V
CC
+125
1000
600
500
400
Unit
V
V
_C
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
≤
2.4mA
|I
out
|
≤
4.0mA
|I
out
|
≤
5.2mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
≤
2.4mA
|I
out
|
≤
4.0mA
|I
out
|
≤
5.2mA
3.0
4.5
6.0
6.0
6.0
Guaranteed Limit
−55 to 25°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
4
≤85°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
40
≤125°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.20
3.70
5.20
0.1
0.1
0.1
0.40
0.40
0.40
±1.0
160
mA
mA
V
Unit
V
Symbol
V
IH
Parameter
Minimum High−Level Input Voltage
Condition
V
out
= 0.1V or V
CC
−0.1V
|I
out
|
≤
20mA
V
IL
Maximum Low−Level Input Voltage
V
out
= 0.1V or V
CC
− 0.1V
|I
out
|
≤
20mA
V
V
OH
Minimum High−Level Output Voltage
V
in
= V
IH
or V
IL
|I
out
|
≤
20mA
V
in
= V
IH
or V
IL
V
V
OL
Maximum Low−Level Output Voltage
V
in
= V
IH
or V
IL
|I
out
|
≤
20mA
V
in
= V
IH
or V
IL
I
in
I
CC
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0mA
http://onsemi.com
2
MC74HC4040A
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
−55 to 25°C
10
15
30
50
96
63
31
25
65
30
30
26
69
40
17
14
75
27
15
13
10
≤85°C
9.0
14
28
45
106
71
36
30
72
36
35
32
80
45
21
15
95
32
19
15
10
≤125°C
8.0
12
25
40
115
88
40
35
90
40
40
35
90
50
28
22
110
36
22
19
10
Unit
MHz
Symbol
f
max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 2 and 5)
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q1*
(Figures 2 and 5)
ns
t
PHL
Maximum Propagation Delay, Reset to Any Q
(Figures 3 and 5)
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Qn to Qn+1
(Figures 4 and 5)
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 2 and 5)
ns
C
in
Maximum Input Capacitance
pF
* For T
A
= 25°C and C
L
= 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
V
CC
= 2.0 V: t
P
= [93.7 + 59.3 (n−1)] ns
V
CC
= 4.5 V: t
P
= [30.25 + 14.6 (n−1)] ns
V
CC
= 3.0 V: t
P
= [61.5 + 34.4 (n−1)] ns
V
CC
= 6.0V: t
P
= [24.4 + 12 (n−1)] ns
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
31
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
TIMING REQUIREMENTS
(Input t
r
= t
f
= 6 ns)
Symbol
t
rec
Parameter
Minimum Recovery Time, Reset Inactive to Clock
(Figure 3)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
−55 to 25°C
30
20
5
4
70
40
15
13
70
40
15
13
1000
800
500
400
≤85°C
40
25
8
6
80
45
19
16
80
45
19
16
1000
800
500
400
≤125°C
50
30
12
9
90
50
24
20
90
50
24
20
1000
800
500
400
Unit
ns
t
w
Minimum Pulse Width, Clock
(Figure 2)
ns
t
w
Minimum Pulse Width, Reset
(Figure 3)
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 2)
ns
http://onsemi.com
3
MC74HC4040A
PIN DESCRIPTIONS
INPUTS
Clock (Pin 10)
OUTPUTS
Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)
Negative−edge triggering clock input. A high−to−low
transition on this input advances the state of the counter.
Reset (Pin 11)
Active−high outputs. Each Qn output divides the Clock
input frequency by 2
N
.
Active−high reset. A high level applied to this input
asynchronously resets the counter to its zero state, thus
forcing all Q outputs low.
SWITCHING WAVEFORMS
t
f
Clock
90%
50%
10%
t
w
1/f
MAX
t
PLH
Q1
90%
50%
10%
t
TLH
t
THL
t
PHL
t
r
V
CC
GND
Reset
t
PHL
Any Q
50%
Clock
t
rec
t
w
50%
GND
50%
GND
V
CC
V
CC
Figure 2.
Figure 3.
TEST
POINT
V
CC
Qn
50%
GND
t
PLH
Qn+1
50%
t
PHL
DEVICE
UNDER
TEST
OUTPUT
C
L
*
*Includes all probe and jig capacitance
Figure 4.
Figure 5. Test Circuit
http://onsemi.com
4
MC74HC4040A
Q1
9
Q2
7
Q3
6
Q10
14
Q11
15
Q12
1
Clock
10
C
Q
C
Q
C
Q
C
Q
C
Q
C
Q
C
R
Reset
11
Q
C
R
Q
C
Q
C
Q
C
Q
C
Q4 = Pin 5
Q5 = Pin 3
Q6 = Pin 2
Q7 = Pin 4
Q8 = Pin 13
Q9 = Pin 12
V
CC
= Pin 16
GND = Pin 8
Figure 6. Expanded Logic Diagram
1
Clock
Reset
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
2
4
8
16
32
64
128
256
512
1024
2048
4096
Figure 7. Timing Diagram
http://onsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
