Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Operating Supply Current
Shutdown Supply Current
Rising 5VSB POR Threshold
5VSB POR Hysteresis
Rising 12V Threshold
Soft-Start Current
Shutdown Soft-Start Voltage
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3
SYMBOL
I
5VSB
I
5VSB(OFF)
V
SS
= 0.8V, S3 = 0, S5 = 0
TEST CONDITIONS
MIN
-
-
-
-
-
-
-
-
V
VSEN2
V
VSEN2
R
SEL
= 1kΩ
R
SEL
= 10kΩ
-
-
-
-
I
VSEN2
I
DRV2
5VSB = 5V
5VSB = 5V, R
SEL
= 1kΩ
R
SEL
= 10kΩ
250
20
-
-
V
3V3DL
-
-
-
I
3V3DLSB
5VSB = 5V
5.0
-
TYP
20
10
-
0.2
-
10
-
-
2.5
3.3
75
6
300
30
200
-
3.3
2.450
200
8.5
90
MAX
-
-
4.5
-
10.8
-
0.8
2.0
-
-
-
-
-
-
-
2.0
-
-
-
-
-
UNITS
mA
mA
V
V
V
µA
V
%
V
V
%
%
mA
mA
Ω
%
V
V
mV
mA
Ω
POWER-ON RESET, SOFT-START, AND 12V MONITOR
2.5V/3.3V LINEAR REGULATOR (V
OUT2
)
Regulation
VSEN2 Nominal Voltage Level
VSEN2 Nominal Voltage Level
VSEN2 Under-voltage Rising Threshold
VSEN2 Under-voltage Hysteresis
VSEN2 Output Current
DRV2 Output Drive Current
DRV2 Output Impedance
3.3VDUAL LINEAR REGULATOR (V
OUT1
)
Sleep-Mode Regulation
3V3DL Nominal Voltage Level
3V3DL Under-voltage Rising Threshold
3V3DL Under-voltage Hysteresis
3V3DLSB Output Drive Current
DLA Output Impedance
4
FN4749.6
December 30, 2004
HIP6501A
Electrical Specifications
PARAMETER
5VDUAL SWITCH CONTROLLER (V
OUT3
)
5VDL Under-Voltage Rising Threshold
5VDL Under-Voltage Hysteresis
5VDLSB Output Drive Current
5VDLSB Pull-up Impedance to 5VSB
TIMING INTERVALS
Active State Assessment Past 12V
Threshold
Maximum Allowable S3 to S5 Skew
5VSB POR Extension Past Threshold
Voltage
CONTROL I/O (S3, S5, EN3VDL, EN5VDL, FAULT)
High Level Threshold
Low Level Threshold
S3,S5 Internal Pull-up Impedance to 5VSB
FAULT Output Impedance
FAULT Under-Voltage Reporting Delay
TEMPERATURE MONITOR
Fault-Level Threshold
Shutdown-Level Threshold
NOTES:
2. Guaranteed by Correlation.
3. Guaranteed by Design.
Note 3
Note 3
125
-
-
150
-
-
°C
°C
FAULT = high
-
0.8
-
-
-
-
-
70
100
10
2.2
-
-
-
-
V
V
kΩ
Ω
µs
Note 2
40
-
-
50
200
3.3
60
-
-
ms
µs
ms
I
5VDLSB
5VDLSB = 4V
-
-
-20
-
3.750
260
-
350
-
-
-40
-
V
mV
mA
Ω
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3
(Continued)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Functional Pin Description
5VSB (Pin 1)
Provide a 5V bias supply for the IC to this pin by connecting
it to the ATX 5VSB output. This pin also provides the base
bias current for all the external NPN transistors controlled by
the IC. The voltage at this pin is monitored for power-on
reset (POR) purposes.
EN3VDL and EN5VDL (Pins 2 and 5)
These pins control the logic governing the output behavior in
response to S3 and S4/S5 requests. These are digital inputs
whose status can only be changed during active states
operation or during chip shutdown (SS pin grounded by
external open-drain device). The input information is
latched-in when entering a sleep state, as well as following
5VSB POR release or exit from shutdown.
GND (Pin 8)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
FAULT/MSEL (Pin 9)
This is a multiplexed function pin allowing the setting of the
memory output voltage to either 2.5V or 3.3V (for RDRAM or
SDRAM memory systems). The memory voltage setting is
latched-in 3ms (typically) after 5VSB POR release. In case
of an under-voltage on any of the outputs or an over-
temperature event, this pin is used to report the fault
condition by being pulled to 5VSB.
S3 and S5 (Pins 6 and 7)
These pins switch the IC’s operating state from active (S0,
S1) to S3 and S4/S5 sleep states. Connect S3 to SLP_S3
and S5 to SLP_S5. These are digital inputs featuring internal
70kΩ (typical) resistor pull-ups to 5VSB. Internal circuitry de-
glitches the S3 pin for disturbances. Additional circuitry
blocks any illegal state transitions (such as S3 to S4/S5 or
vice versa). When entering an S4/S5 sleep state, the S3
signal is allowed to go low as far as 200µs (typically) ahead
of the S5 signal.
SS (Pin 13)
Connect a small ceramic capacitor (allowable range: 5nF-
0.22µF; 0.1µF recommended) from this pin to GND. The
internal Soft-Start (SS) current source along with the
external capacitor creates a voltage ramp used to control the
ramp-up of the output voltages. Pulling this pin low with an
open-drain device shuts down all the outputs as well as
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