100% pin-to-pin drop-in replacement to quartz-based XO
Excellent total frequency stability as low as ±20 ppm
Operating temperature from -40°C to 85°C. For 125°C and/or
-55°C options, refer to
SiT8919
and
SiT8921
Low power consumption of 4.9 mA typical at 1.8V
Standby mode for longer battery life
Fast startup time of 5 ms
LVCMOS/HCMOS compatible output
Industry-standard packages: 2.0 x 1.6, 2.5 x 2.0, 3.2 x 2.5,
5.0 x 3.2, 7.0 x 5.0 mm x mm
Instant samples with
Time Machine II
and
field programmable
oscillators
RoHS and REACH compliant, Pb-free, Halogen-free and
Antimony-free
For AEC-Q100 oscillators, refer to
SiT8924
and
SiT8925
Ideal for GPON/GPON, network switches, routers.
servers, embedded systems
Ideal for Ethernet, PCI-E, DDR, etc.
Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and nominal supply voltage.
Table 1. Electrical Characteristics
Parameters
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
115
-20
-25
-50
Operating Temperature Range
T_use
-20
-40
Supply Voltage
Vdd
1.62
2.25
2.52
2.7
2.97
2.25
Current Consumption
Idd
–
–
–
OE Disable Current
Standby Current
I_OD
I_std
–
–
–
–
–
Duty Cycle
Rise/Fall Time
DC
Tr, Tf
45
–
–
–
Output High Voltage
Output Low Voltage
VOH
VOL
90%
–
Typ.
–
–
–
–
–
–
Max.
137
+20
+25
+50
+70
+85
Unit
MHz
ppm
ppm
ppm
°C
°C
Extended Commercial
Industrial
Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C, and
variations over operating temperature, rated power supply
voltage and load.
Condition
Frequency Range
Frequency Stability and Aging
Operating Temperature Range
Supply Voltage and Current Consumption
Contact
SiTime
for 1.5V support
1.8
1.98
V
2.5
2.8
3.0
3.3
–
6.2
5.5
4.9
–
–
2.6
1.4
0.6
–
1
1.3
0.8
–
–
2.75
3.08
3.3
3.63
3.63
7.5
6.4
5.6
4.2
4.0
4.3
2.5
1.3
55
2
2.5
2
–
10%
V
V
V
V
V
mA
mA
mA
mA
mA
A
A
A
%
ns
ns
ns
Vdd
Vdd
No load condition, f = 125 MHz, Vdd = 2.8V, 3.0V, 3.3V or 2.25
to 3.63V
No load condition, f = 125 MHz, Vdd = 2.5V
No load condition, f = 125 MHz, Vdd = 1.8V
Vdd = 2.5V to 3.3V, OE = GND, Output in high-Z state
Vdd = 1.8V, OE = GND, Output in high-Z state
ST = GND, Vdd = 2.8V to 3.3V, Output is weakly pulled down
ST = GND, Vdd = 2.5V, Output is weakly pulled down
ST = GND, Vdd = 1.8V, Output is weakly pulled down
All Vdds
Vdd = 2.5V, 2.8V, 3.0V or 3.3V, 20% - 80%
Vdd =1.8V, 20% - 80%
Vdd = 2.25V - 3.63V, 20% - 80%
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOL = 4 mA (Vdd = 3.0V or 3.3V)
LVCMOS Output Characteristics
Rev 1.04
January 11, 2017
www.sitime.com
SiT8009B
High Frequency, Low Power Oscillator
Table 1. Electrical Characteristics (continued)
Parameters
Input High Voltage
Input Low Voltage
Input Pull-up Impedance
Symbol
VIH
VIL
Z_in
Min.
70%
–
50
2
Startup Time
Enable/Disable Time
Resume Time
RMS Period Jitter
Peak-to-peak Period Jitter
RMS Phase Jitter (random)
T_start
T_oe
T_resume
T_jitt
T_pk
T_phj
–
–
–
–
–
–
–
–
–
Typ.
–
–
87
Max.
–
30%
150
Unit
Vdd
Vdd
k
Pin 1, OE or ST
Pin 1, OE or ST
Pin 1, OE logic high or logic low, or ST logic high
Condition
Input Characteristics
–
–
Pin 1, ST logic low
M
Startup and Resume Timing
–
–
–
1.9
1.8
12
14
0.5
1.3
5
122
5
Jitter
3
4
25
30
0.9
2
ps
ps
ps
ps
ps
ps
f = 125 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
f = 125 MHz, Vdd = 1.8V
f = 125 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
f = 125 MHz, Vdd = 1.8V
Integration bandwidth = 900 kHz to 7.5 MHz
Integration bandwidth = 12 kHz to 20 MHz
ms
ns
ms
Measured from the time Vdd reaches its rated minimum value
f = 137 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles
Measured from the time ST pin crosses 50% threshold
Table 2. Pin Description
Pin
Symbol
[1]
Functionality
Output Enable
H : specified frequency output
L: output is high impedance. Only output driver is disabled.
H
[1]
: specified frequency output
L: output is low (weak pull down). Device goes to sleep mode. Supply
current reduces to I_std.
Any voltage between 0 and Vdd or Open
[1]
: Specified frequency
output. Pin 1 has no function.
Electrical ground
Oscillator output
Power supply voltage
[2]
OE/ST/NC
1
Top View
4
VDD
1
OE/ST/NC
Standby
No Connect
2
3
4
GND
OUT
VDD
Power
Output
Power
GND
2
3
OUT
Figure 1. Pin Assignments
Notes:
1. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option.
2. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Rev. 1.04
Page 2 of 17
www.sitime.com
SiT8009B
High Frequency, Low Power Oscillator
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance
of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
Vdd
Electrostatic Discharge
Soldering Temperature (follow standard Pb free
soldering guidelines)
Junction Temperature
[3]
Min.
-65
-0.5
–
–
–
Max.
150
4
2000
260
150
Unit
°C
V
V
°C
°C
Note:
3. Exceeding this temperature for extended period of time may damage the device.
Table 4. Thermal Consideration
[4]
Package
7050
5032
3225
2520
2016
JA, 4 Layer Board
(°C/W)
142
97
109
117
152
JA, 2 Layer Board
(°C/W)
273
199
212
222
252
JC, Bottom
(°C/W)
30
24
27
26
36
Note:
4. Refer to JESD51 for
JA
and
JC
definitions, and reference layout used to determine the
JA
and
JC
values in the above table.
Table 5. Maximum Operating Junction Temperature
[5]
Max Operating Temperature (ambient)
70°C
85°C
Maximum Operating Junction Temperature
80°C
95°C
Note:
5. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.04
Page 3 of 17
www.sitime.com
SiT8009B
High Frequency, Low Power Oscillator
Test Circuit and Waveform
[6]
Vdd
Vout
Test
Point
tr
80% Vdd
tf
4
Power
Supply
0.1µF
1
3
15pF
(including probe
and fixture
capacitance)
50%
20% Vdd
High Pulse
(TH)
Period
Low Pulse
(TL)
2
Vdd
OE/ST Function
1k
Figure 2. Test Circuit
Note:
6. Duty Cycle is computed as Duty Cycle = TH/Period.
Figure 3. Waveform
Timing Diagrams
Vdd
Vdd
90% Vdd
[7]
50% Vdd
ST Voltage
T_resume
T_start
Pin 4 Voltage
No Glitch
during start up
CLK Output
HZ
CLK Output
HZ
T_start: Time to start from power-off
T_resume: Time to resume from ST
Figure 4. Startup Timing (OE/ST Mode)
Figure 5. Standby Resume Timing (ST Mode Only)
Vdd
50% Vdd
OE Voltage
OE Voltage
T_oe
Vdd
50% Vdd
T_oe
CLK Output
HZ
T_oe: Time to re-enable the clock output
CLK Output
HZ
T_oe: Time to put the output in High Z mode
Figure 6. OE Enable Timing (OE Mode Only)
Note:
7. SiT8009 has “no runt” pulses and “no glitch” output during startup or resume.
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