Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
HYB25D128160C[E/F/T], HYB25D128400C[C/E/T]
Revision History: 2006-09, Rev. 1.51
Page
All
All
5
11
74
Subjects (major changes since last revision)
Qimonda update
Adapted internet edition
Removed product type HYB25D128800CTL-6 and HYB25D128800CE-6
Added product type HYB25D128800CE-5, HYB25D128800CC-5 and HYB25D128800CC-6
Changed for D11 tRFC(DDR400) from 70 ns to 65 ns as programmed in byte 42 SPD Code
Previous Revision: 2006-02, Rev. 1.5
Previous Revision: 2005-11, Rev. 1.4
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
03292006-U5AN-6TI1
2
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
1
1.1
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Overview
Features
This chapter contains features and the description.
Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Burst Lengths: 2, 4, or 8
CAS Latency: 2, 2.5, 3
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported
t
RAP
=
t
RCD
7.8
µs
Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
V
DDQ
= 2.5 V
±
0.2 V (DDR266A, DDR333);
V
DDQ
= 2.6 V
±
0.1 V (DDR400)
V
DD
= 2.5 V
±
0.2 V (DDR266A, DDR333);
V
DD
= 2.6 V
±
0.1 V (DDR400)
P(G)-TFBGA-60 package with 3 depopulated rows (8
×
12 mm
2
)
P(G)-TSOPII-66 package
Lead- and halogene-free = green product
TABLE 1
Performance
Part Number Speed Code
Speed Grade
max. Clock Frequency
Component
Module
@CL3
@CL2.5
@CL2
–5
DDR400B
PC3200-3033
–6
DDR333
PC2700–2533
166
166
133
–7
DDR266A
PC2100-2033
—
143
133
Unit
—
—
MHz
MHz
MHz
f
CK3
f
CK2.5
f
CK2
200
166
133
Rev. 1.51, 2006-09
03292006-U5AN-6TI1
3
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
1.2
Description
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write
command. The address bits registered coincident with the
Active command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank
architecture of
DDR SDRAMs allows for concurrent
operation, thereby providing high effective bandwidth by
hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II
compatible.
Note: The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
The 128-Mbit Double-Data-Rate SDRAM is a high-speed
CMOS, dynamic random-access memory containing
134,217,728 bits. It is internally configured as a quad-bank
DRAM.
The 128-Mbit Double-Data-Rate SDRAM uses a double-
data-rate architecture to achieve high-speed operation. The
double data rate architecture is essentially a
2n
prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access
for
the
128-Mbit Double-Data-Rate SDRAM
effectively consists of a single
2n-bit
wide, one clock cycle
data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 128-Mbit Double-Data-Rate SDRAM operates from a
differential clock (CK and CK; the crossing of CK going HIGH
and CK going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Rev. 1.51, 2006-09
03292006-U5AN-6TI1
4
Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 2
Ordering Informationfor non RoHS Compliant Products
Part Number
1)
HYB25D128160CT–5
HYB25D128800CT–6
HYB25D128160CT–6
HYB25D128400CT–7
HYB25D128800CC–5
HYB25D128400CC–6
HYB25D128800CC–6
Org.
×16
×8
×16
×4
×8
×4
×8
3-3-3
2.5-3-3
143
200
166
2.5-3-3
2-3-3
166
133
DDR266A
DDR400B
DDR333
P-FBGA-60-12
CAS-RCD-
Clock
RP Latencies (MHz)
3-3-3
2.5-3-3
200
166
CAS-RCD-RP Clock
Latencies
(MHz)
2.5-3-3
2-3-3
166
133
Speed
DDR400B
DDR333
Package
P-TSOPII-66-2
Note
2)
TABLE 3
Order Information for RoHS Compliant Products
Part Number
1)
HYB25D128160CE–5
HYB25D128800CE–5
HYB25D128800CF–5
HYB25D128160CE–6
HYB25D128400CE–6
HYB25D128800CE–6
HYB25D128800CF–6
HYB25D128400CE–7
×4
143
×16
×4
×8
PG-FBGA-60-19
DDR266A PG-TSOPII-66-1
2.5-3-3
166
2-3-3
133
DDR333
Org.
×16
×8
PG-FBGA-60-19
PG-TSOPII-66-1
CAS-RCD-RP
Latencies
3-3-3
Clock CAS-RCD-RP
(MHz) Latencies
200
2.5-3-3
Clock
(MHz)
166
Speed
Package
Note
2)
DDR400B PG-TSOPII-66-1
1) HYB: designator for memory components 25D: DDR SDRAMs at
V
DDQ
= 2.5 V 128: 128-Mbit density 400/800/160: Product variations
×4,
×8
and
×16
C: Die revision C T/E/C: Package type TSOP and FBGA L: Low power version (available on request) - these components are
specifically selected for low
I
DD6
Self Refresh currents -5/6/7/7F/8: speed grade - see
Table 2
2) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.51, 2006-09
03292006-U5AN-6TI1
5
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