September 2007
HY[B/I]39S256[40/80/16]0FT(L)
HY[B/I]39S256[40/80/16]0FE(L)
HYB39S256[40/80/16]0FF(L)
H Y B 39 S 256 407F E
256-MBit Synchronous DRAM
SDRAM
Internet Data Sheet
Rev. 1.42
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
HY[B/I]39S256[40/80/16]0FT(L), HY[B/I]39S256[40/80/16]0FE(L), HYB39S256[40/80/16]0FF(L), HYB39S256407FE
Revision History: 2007-09, Rev. 1.42
Page
All
7
All
4
4
Subjects (major changes since last revision)
Adapted internet edition
Corrected SDRAM organization for x4 in Table 4
Editorial Change
Corrected HYB39S256407FF-7 to HYP39S256407FE-7
Corrected HYB39S256400FE-7 to HYB39S256400FF-7
Previous Revision: 2007-09, Rev. 1.41
Previous Revision: 2007-04, Rev. 1.40
Previous Revision: 2007-03, Rev. 1.30
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
03292006-TMTK-JFEU
2
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
1
1.1
•
•
•
•
•
•
•
•
•
•
Overview
Features
•
•
•
•
•
•
•
•
Data Mask for Byte Control (x16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
8192 refresh cycles / 64 ms (7.8
μs)
Random Column Address every CLK (1-N Rule)
Single 3.3 V ± 0.3 V Power Supply
LVTTL Interface versions
Packages:
– P(G)–TSOPII–54 (400mil width)
– PG–TFBGA–54
This chapter lists all main features of the product family HYB39S256[400/800/160]F[E/T/F](L) and the ordering information.
Fully Synchronous to Positive Clock Edge
0 to 70
°C
Standard Operating Temperature
-40 to 85
°C
Industrial Operating Temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length: 1, 2, 4, 8 and full page
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Data Mask for Read / Write control (x4, x8)
TABLE 1
Performance
Poduct Type Speed Code
Speed Grade
Max. Clock Frequency
@CL3
–6
PC166–333
–7
PC133–222
143
7
5.4
7.5
5.4
Unit
—
MHz
ns
ns
ns
ns
@CL2
f
CK3
t
CK3
t
AC3
t
CK2
t
AC2
166
6
5.4
7.5
5.4
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
3
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
1.2
Description
The HYB39S256[400/800/160]F[E/T/F](L) are four bank Synchronous DRAMs organized as 4 banks x 16 MBit x4,
4 banks x 8 MBit x8 and 4 banks x 4 Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates
for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a
system clock. The chip is fabricated with Qimonda’s advanced 0.11-μm 256-MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally
supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is
possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and
speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V power supply.
All 256-Mbit components are available in P(G)–TSOPII–54 and PG–TFBGA–54 packages.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
HYB39S256407FE-7
HYB39S256400FF-7
HYB39S256400FE-7
HYB39S256400FFL-7
HYB39S256400FEL-7
HYB39S256800FF-7
HYB39S256800FE-7
HYB39S256800FFL-7
HYB39S256800FEL-7
HYB39S256160FF-7
HYB39S256160FE-7
HYB39S256160FFL-7
HYB39S256160FEL-7
HYB39S256160FF-6
HYB39S256160FE-6
HYB39S256160FFL-6
HYB39S256160FEL-6
Industrial Operating Temperature
HYI39S256800FE-7
HYI39S256160FE-7
PC166-333
143MHz 32M x 8 SDRAM
143MHz 16M x 16 SDRAM
PG-TSOPII-54
1)
Speed Grade
PC133-222
Description
143MHz 64M x 4 SDRAM
Package
PG-TFBGA-54
PG-TFBGA-54
PG-TSOPII-54
PG-TFBGA-54
PG-TSOPII-54
Note
1)
Standard Operating Temperature
143MHz 32M x 8 SDRAM
PG-TFBGA-54
PG-TSOPII-54
PG-TFBGA-54
PG-TSOPII-54
143MHz 16M x 16 SDRAM
PG-TFBGA-54
PG-TSOPII-54
PG-TFBGA-54
PG-TSOPII-54
166MHz 16M x 16 SDRAM
PG-TFBGA-54
PG-TSOPII-54
PG-TFBGA-54
PG-TSOPII-54
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
4
Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
TABLE 3
Ordering Information for Lead-Containing Products
Product Type
HYB39S256400FT-7
HYB39S256400FTL-7
HYB39S256800FT-7
HYB39S256800FTL-7
HYB39S256160FT-7
HYB39S256160FTL-7
HYB39S256160FT-6
Industrial Operating Temperature
HYI39S256800FT-7
HYI39S256160FT-7
PC133-222
143MHz 32M x 8 SDRAM
143MHz 16M x 16 SDRAM
P-TSOPII-54
166MHz 16M x 16 SDRAM
143MHz 16M x 16 SDRAM
143MHz 32M x 8 SDRAM
Speed Grade
PC133-222
Description
143MHz 64M x 4 SDRAM
Package
P-TSOPII-54
Standard Operating Temperature
Note: For product nomenclature see
Chapter 6
of this data sheet
Rev. 1.42, 2007-09
03292006-TMTK-JFEU
5
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