Intel
®
Xeon
®
Processor E3-1200 v4
Product Family
Datasheet – Volume 1 of 2
June 2015
Reference Number: 332374-002US
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2
Datasheet, Volume 1 of 2
Table of Contents
1
Introduction
............................................................................................................ 11
1.1
Supported Technologies ..................................................................................... 12
1.2
Interfaces ........................................................................................................ 13
1.3
Power Management Support ............................................................................... 13
1.3.1 Processor Core....................................................................................... 13
1.3.2 System ................................................................................................. 13
1.3.3 Memory Controller.................................................................................. 13
1.3.4 PCI Express* ......................................................................................... 13
1.3.5 DMI...................................................................................................... 13
1.3.6 Processor Graphics Controller................................................................... 14
1.4
Thermal Management Support ............................................................................ 14
1.5
Package Support ............................................................................................... 14
1.6
Processor Testability .......................................................................................... 14
1.7
Terminology ..................................................................................................... 14
1.8
Related Documents ........................................................................................... 18
Interfaces................................................................................................................
19
2.1
System Memory Interface .................................................................................. 19
2.1.1 System Memory Technology Supported ..................................................... 20
2.1.2 System Memory Timing Support............................................................... 21
2.1.3 System Memory Organization Modes......................................................... 21
2.1.3.1 System Memory Frequency ........................................................ 23
2.1.3.2 Intel® Fast Memory Access (Intel® FMA) Technology Enhancements...
23
2.1.3.3 Data Scrambling ....................................................................... 23
2.2
PCI Express* Interface....................................................................................... 24
2.2.1 PCI Express* Support ............................................................................. 24
2.2.2 PCI Express* Architecture ....................................................................... 25
2.2.3 PCI Express* Configuration Mechanism ..................................................... 26
2.2.3.1 PCI Express* Port ..................................................................... 26
2.2.3.2 PCI Express* Lanes Connection .................................................. 26
2.3
Direct Media Interface (DMI)............................................................................... 27
2.3.1 DMI Error Flow....................................................................................... 28
2.3.2 DMI Link Down ...................................................................................... 28
2.4
Processor Graphics ............................................................................................ 28
2.5
Processor Graphics Controller (GT) ...................................................................... 29
2.5.1 3D and Video Engines for Graphics Processing............................................ 30
2.5.2 Multi Graphics Controllers Multi-Monitor Support......................................... 32
2.6
Digital Display Interface (DDI) ............................................................................ 32
2.7
Intel® Flexible Display Interface (Intel® FDI) ....................................................... 38
2.8
Platform Environmental Control Interface (PECI) ................................................... 38
2.8.1 PECI Bus Architecture ............................................................................. 38
Technologies
........................................................................................................... 41
3.1
Intel
®
Virtualization Technology (Intel
®
VT) ......................................................... 41
3.1.1 Intel
®
VT-x Objectives ............................................................................ 41
3.1.2 Intel
®
VT-x Features .............................................................................. 42
3.1.3 Intel
®
VT-d Objectives ............................................................................ 43
3.1.4 Intel
®
VT-d Features .............................................................................. 45
3.2
Intel
®
Trusted Execution Technology (Intel
®
TXT) ................................................. 46
3.3
Intel
®
Hyper-Threading Technology (Intel
®
HT Technology).................................... 47
3.4
Intel
®
Turbo Boost Technology 2.0 ...................................................................... 47
3.4.1 Intel
®
Turbo Boost Technology 2.0 Frequency............................................ 47
3.5
Intel
®
Advanced Vector Extensions 2.0 (Intel
®
AVX2) ............................................ 48
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Datasheet, Volume 1 of 2
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3.6
3.7
3.8
3.9
3.10
3.11
4
3.5.1
AVX Disclaimer
....................................................................................48
Intel
®
Advanced Encryption Standard New Instructions (Intel
®
AES-NI) ...................48
3.6.1 PCLMULQDQ Instruction ..........................................................................49
3.6.2 Intel
®
Secure Key...................................................................................49
Intel
®
Transactional Synchronization Extensions - New Instructions (Intel
®
TSX-NI)...49
Intel
®
64 Architecture x2APIC .............................................................................49
Power Aware Interrupt Routing (PAIR)..................................................................50
Execute Disable Bit ............................................................................................51
Supervisor Mode Execution Protection (SMEP) .......................................................51
Power Management
.................................................................................................53
4.1
Advanced Configuration and Power Interface (ACPI) States Supported ......................54
4.2
Processor Core Power Management ......................................................................55
4.2.1 Enhanced Intel SpeedStep® Technology Key Features.................................56
4.2.2 Low-Power Idle States.............................................................................56
4.2.3 Requesting Low-Power Idle States ............................................................58
4.2.4 Core C-State Rules .................................................................................58
4.2.5 Package C-States ...................................................................................60
4.2.6 Package C-States and Display Resolution ...................................................63
4.3
Integrated Memory Controller (IMC) Power Management.........................................64
4.3.1 Disabling Unused System Memory Outputs.................................................64
4.3.2 DRAM Power Management and Initialization ...............................................65
4.3.2.1 Initialization Role of CKE ............................................................66
4.3.2.2 Conditional Self-Refresh .............................................................66
4.3.2.3 Dynamic Power-Down ................................................................66
4.3.2.4 DRAM I/O Power Management ....................................................66
4.3.3 DRAM Running Average Power Limitation (RAPL).........................................67
4.3.4 DDR Electrical Power Gating (EPG) ............................................................67
4.4
PCI Express* Power Management ........................................................................67
4.5
Direct Media Interface (DMI) Power Management ...................................................67
4.6
Graphics Power Management...............................................................................67
4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM) ............................67
4.6.2 Graphics Render C-State .........................................................................67
4.6.3 Intel® Graphics Dynamic Frequency .........................................................68
Thermal Specifications Map......................................................................................69
5.1
Processor Thermal Profiles ..................................................................................71
5.1.1 Processor (80W) Thermal Profile ...............................................................72
5.1.2 Processor (65W) Thermal Profile ...............................................................74
5.1.3 Processor (35W) Thermal Profile ...............................................................75
5.2
Thermal Metrology .............................................................................................76
5.3
Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 1.1 ...........................77
5.4
Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0 ...........................79
5.5
Product Family Thermal Specifications ..................................................................80
5.5.1 Performance Targets ...............................................................................80
5.6
Processor Temperature.......................................................................................81
5.7
Adaptive Thermal Monitor ...................................................................................81
5.7.1 Frequency Control...................................................................................82
5.7.2 Clock Modulation ....................................................................................83
5.7.3 Immediate Transition to Combined TM1 and TM2 ........................................83
5.7.4 Critical Temperature Flag .........................................................................83
5.7.5 PROCHOT# Signal ..................................................................................84
5.8
THERMTRIP# Signal ...........................................................................................85
5.9
Digital Thermal Sensor .......................................................................................85
5.9.1 Digital Thermal Sensor Accuracy (Taccuracy)..............................................86
5.10 Intel
®
Turbo Boost Technology Thermal Considerations ..........................................86
5.11 Intel
®
Turbo Boost Technology Power Control and Reporting ...................................86
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Datasheet, Volume 1 of 2
5.11.1 Package Power Control............................................................................ 87
6
Signal Description
................................................................................................... 89
6.1
System Memory Interface Signals........................................................................ 89
6.2
Memory Reference and Compensation .................................................................. 91
6.3
Reset and Miscellaneous Signals.......................................................................... 92
6.4
PCI Express*-Based Interface Signals .................................................................. 93
6.5
Display Interface Signals .................................................................................... 93
6.6
Direct Media Interface (DMI)............................................................................... 93
6.7
Phase Locked Loop (PLL) Signals ......................................................................... 94
6.8
Testability Signals ............................................................................................. 94
6.9
Error and Thermal Protection Signals ................................................................... 95
6.10 Power Sequencing Signals .................................................................................. 95
6.11 Processor Power Signals ..................................................................................... 96
6.12 Sense Signals ................................................................................................... 96
6.13 Ground and Non-Critical to Function (NCTF) Signals ............................................... 96
6.14 Processor Internal Pull-Up / Pull-Down Terminations .............................................. 97
Electrical Specifications
........................................................................................... 99
7.1
Integrated Voltage Regulator .............................................................................. 99
7.2
Power and Ground Lands.................................................................................... 99
7.3
VCC Voltage Identification (VID).......................................................................... 99
7.4
Reserved or Unused Signals.............................................................................. 106
7.5
Signal Groups ................................................................................................. 107
7.6
Test Access Port (TAP) Connection..................................................................... 109
7.7
DC Specifications ............................................................................................ 109
7.8
Voltage and Current Specifications..................................................................... 110
7.8.1 PECI DC Characteristics......................................................................... 115
7.8.2 Input Device Hysteresis ........................................................................ 116
7.9
AC Specifications............................................................................................. 116
7.10 Processor AC Timing Waveforms ....................................................................... 126
7.11 Signal Quality ................................................................................................. 130
7.12 Overshoot / Undershoot Guidelines .................................................................... 131
7.12.1 VCC Overshoot Specification .................................................................. 131
7.12.2 Overshoot / Undershoot Magnitude......................................................... 131
7.12.3 Overshoot / Undershoot Pulse Duration ................................................... 131
Package Mechanical Specifications
........................................................................ 133
8.1
Package Mechanical Drawing............................................................................. 133
8.2
Processor Component Keep-Out Zone ................................................................ 133
8.3
Package Loading Specifications ......................................................................... 134
8.4
Package Handling Guidelines............................................................................. 134
8.5
Package Insertion Specifications........................................................................ 134
8.6
Processor Mass Specification ............................................................................. 134
8.7
Processor Materials.......................................................................................... 135
8.8
Processor Markings.......................................................................................... 135
8.9
Processor Land Coordinates .............................................................................. 135
8.10 Processor Storage Specifications ....................................................................... 136
Processor Ball and Signal Information
................................................................... 139
DDR Data Swizzling
............................................................................................... 149
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Datasheet, Volume 1 of 2
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