S i 5 11 0
SiPHY
OC-48/STM-16 SONET/SDH T
RANSCEIVER
Features
Complete low-power, high-speed, SONET/SDH transceiver
integrated limiting amp, CDR, CMU, and MUX/DEMUX.
with
Si5110
Data rates supported:
SONET-compliant loop-timed
OC-48/STM-16 through 2.7 Gbps
operation
FEC
Programmable slicing level and
sample phase adjustment
Low-power operation 1.0 W (typ)
DSPLL
based clock multiplier unit
LVDS parallel interface
Single supply 1.8 V operation
with selectable loop filter
bandwidths
11 x 11 mm BGA package
Integrated limiting amplifier
Diagnostic and line loopbacks
Bottom View
Ordering Information:
See page 32.
Applications
SONET/SDH transmission
systems
Optical transceiver modules
SONET/SDH test equipment
Description
The Si5110 is a complete low-power transceiver for high-speed serial
communication systems operating between OC-48 and 2.7 Gbps. The
receive path consists of a fully-integrated limiting amplifier, clock and data
recovery unit (CDR), and 1:4 deserializer. The transmit path combines a
low-jitter clock multiplier unit (CMU) with a 4:1 serializer. The CMU uses
Silicon Laboratories’ DSPLL
technology to provide superior jitter
performance while reducing design complexity by eliminating external
loop filter components. To simplify BER optimization in long haul
applications, programmable slicing and sample phase adjustment are
supported. The Si5110 operates from a single 1.8 V supply over the
industrial temperature range (–20 to 85 °C).
Functional Block Diagram
SLICELVL
PHASEADJ
1:4
DEMUX
RXDIN
Limiting
AMP
RXDOUT[3:0]
Diagnostic
Loopback
RXCLK
÷
CDR
Line
Loopback
4:1
MUX
TXDOUT
TXDIN[3:0]
TXCLKOUT
M
DSPLL
T
TX CMU
TXCLK4IN
REFCLK
BWSEL[1:0]
Rev. 1.5 11/12
Copyright © 2012 by Silicon Laboratories
Si5110
Si5110
T
ABLE O F
C
ONTENTS
Section
Page
1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1. Receiver Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2. Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5.3. Clock and Data Recovery (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4. Deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5. Voltage Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.6. Auxiliary Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7. Receive Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1. DSPLL
®
Clock Multiplier Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2. Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7. Loop Timed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
8. Diagnostic Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9. Line Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
12. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
13. Transmit Differential Output Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
14. Internal Pullups and Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15. Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
16. Si5110 Pinout: 99 BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
17. Pin Descriptions: Si5110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
18. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
19. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
20. 11x11 mm 99L PBGA Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Rev. 1.5
3
Si5110
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
LVTTL I/O Supply Voltage
Si5110 Supply Voltage
Symbol
T
A
V
DDIO
V
DD
Test Condition
Min
*
–20
1.71
1.71
Typ
25
—
1.8
Max
*
85
3.47
1.89
Unit
°C
V
V
*Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25
C
unless otherwise stated.
V
SIGNAL +
Differential
V
ICM
, V
OCM
SIGNAL –
I/Os
0V
(SIGNAL+) – (SIGNAL–)
Differential
Voltage Swing
V
V
ID
,V
OD
(V
ID
= 2 V
ISE
)
Differential Peak-to-Peak Voltage
t
V
I
V
ISE
, V
OSE
Single Ended Voltage
Figure 1. Differential Voltage Measurement
(RXDIN, RXDOUT, RXCLK1, RXCLK2, TXDIN, TXDOUT, TXCLKOUT, TXCLK4OUT, TXCLK4IN)
t
CD
TXDOUT,
TXDIN
t
CP
t
CH
TXCLKOUT,
TXCLK4IN
RXDOUT
RXCLK1
t
cq1
t
cq2
Figure 2. Data to Clock Delay
Rev. 1.5
5
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