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IS61LPS51236B-200TQLI-TR

产品描述SRAM 18Mb, 200Mhz 512K x 36 Sync SRAM
产品类别存储   
文件大小1MB,共33页
制造商ISSI(芯成半导体)
官网地址http://www.issi.com/
标准
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IS61LPS51236B-200TQLI-TR概述

SRAM 18Mb, 200Mhz 512K x 36 Sync SRAM

IS61LPS51236B-200TQLI-TR规格参数

参数名称属性值
Product AttributeAttribute Value
制造商
Manufacturer
ISSI(芯成半导体)
产品种类
Product Category
SRAM
RoHSDetails
Memory Size18 Mbit
Organization512 k x 36
Access Time3 ns
Maximum Clock Frequency200 MHz
电源电压-最大
Supply Voltage - Max
3.465 V
电源电压-最小
Supply Voltage - Min
3.135 V
Supply Current - Max240 mA
最小工作温度
Minimum Operating Temperature
- 40 C
最大工作温度
Maximum Operating Temperature
+ 85 C
安装风格
Mounting Style
SMD/SMT
封装 / 箱体
Package / Case
TQFP-100
系列
Packaging
Reel
Memory TypeSynchronous SRAM
Moisture SensitiveYes
工厂包装数量
Factory Pack Quantity
800
单位重量
Unit Weight
0.288894 oz

文档预览

下载PDF文档
IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED
SINGLE CYCLE DESELECT STATIC RAM
AUGUST 2017
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Burst sequence control using MODE input
Three chip enable option for simple depth
expansion and address pipelining
Common data inputs and data outputs
Auto Power-down during deselect
Single cycle deselect
Snooze MODE for reduced-power standby
JEDEC 100-pin QFP, 165-ball BGA and 119-ball
BGA packages
Power supply:
LPS: V
DD
3.3V (± 5%), V
DDQ
3.3V/2.5V (± 5%)
VPS: V
DD
2.5V (± 5%), V
DDQ
2.5V (± 5%)
VVPS: V
DD
1.8V (± 5%), V
DDQ
1.8V (± 5%)
JTAG Boundary Scan for BGA packages
Commercial, Industrial and Automotive
temperature support
Lead-free available
For leaded options, please contact ISSI
DESCRIPTION
The 18Mb product family features high-speed, low-
power synchronous static RAMs designed to provide
burstable, high-performance memory for
communication and networking applications. The
IS61LPS/VPS/VVPS51236B are organized as 524,288
words by 36bits. The IS61LPS/VPS/VVPS102418B are
organized as 1,048,576 words by 18bits. Fabricated
with ISSI's advanced CMOS technology, the device
integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single
monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock input. Write cycles can
be one to four bytes wide as controlled by the write
control inputs.
Separate byte enables allow individual bytes to be
written. The byte write operation is performed by using
the byte write enable (/BWE) input combined with one
or more individual byte write signals (/BWx). In
addition, Global Write (/GW) is available for writing all
bytes at one time, regardless of the byte write controls.
Bursts can be initiated with either /ADSP (Address
Status Processor) or /ADSC (Address Status Cache
Controller) input pins. Subsequent burst addresses can
be generated internally and controlled by the /ADV
(burst address advance) input pin.
The mode pin is used to select the burst sequence
order. Linear burst is achieved when this pin is tied
LOW. Interleave burst is achieved when this pin is tied
HIGH or left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access
Time
Cycle time
Frequency
-250
2.6
4
250
-200
3.0
5
200
Units
ns
ns
MHz
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D
07/31/2017
1

IS61LPS51236B-200TQLI-TR相似产品对比

IS61LPS51236B-200TQLI-TR IS61VPS51236B-200B3LI-TR IS61VPS51236B-200TQLI-TR IS61VPS51236B-200B3LI IS61VPS51236B-250B3LI IS61LPS102418B IS61LPS102418B-200B3LI IS61VPS51236B-250B3LI-TR IS61LPS51236B-200B3LI-TR IS61VPS102418B-200TQLI
描述 SRAM 18Mb, 200Mhz 512K x 36 Sync SRAM SRAM 18Mb,Pipeline,Sync,512K x 36,200MHz,2.5V I/O,165 Ball BGA, RoHS SRAM 18Mb,Pipeline,Sync,512K x 36,200MHz,2.5V I/O,100 Pin TQFP,RoHS SRAM 18Mb,Pipeline,Sync,512K x 36,200MHz,2.5V I/O,165 Ball BGA, RoHS SRAM 18Mb,Pipeline,Sync,512K x 36,250MHz,2.5V I/O,165 Ball BGA, RoHS SRAM SRAM 18Mb 200MHz, 3.3V or 2.5V 1Mx18 Sync SRAM SRAM 18Mb,Pipeline,Sync,512K x 36,250MHz,2.5V I/O,165 Ball BGA, RoHS SRAM 18Mb, 200Mhz 512K x 36 Sync SRAM SRAM 18Mb PipeSync 1Mbx18 200MHz 3.3V
Product Attribute Attribute Value Attribute Value Attribute Value Attribute Value Attribute Value Attribute Value Attribute Value Attribute Value Attribute Value Attribute Value
制造商
Manufacturer
ISSI(芯成半导体) ISSI(芯成半导体) ISSI(芯成半导体) ISSI(芯成半导体) ISSI(芯成半导体) ISSI(芯成半导体) ISSI(芯成半导体) ISSI(芯成半导体) ISSI(芯成半导体) ISSI(芯成半导体)
产品种类
Product Category
SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM
封装 / 箱体
Package / Case
TQFP-100 FBGA-165 TQFP-100 FBGA-165 FBGA-165 - FBGA-165 FBGA-165 FBGA-165 TQFP-100
Moisture Sensitive Yes Yes Yes Yes Yes - Yes Yes Yes Yes
工厂包装数量
Factory Pack Quantity
800 2000 800 144 144 - 144 2000 2000 72
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