IDT74FCT162374AT/CT/ET
FAST CMOS 16-BIT REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 16-BIT
REGISTER (3-STATE)
IDT74FCT162374AT/CT/ET
FEATURES:
•
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK(o)
(Output Skew) < 250ps
Low input and output leakage
≤
1µA (max.)
V
CC
= 5V ±10%
Balanced Output Drivers: ±24mA
Reduced system switching noise
Typical VOLP (Output Ground Bounce) < 0.6V at V
CC
= 5V,
T
A
= 25°C
• Available in SSOP and TSSOP packages
DESCRIPTION:
The FCT162374T 16-bit edge-triggered D-type registers are built using
advanced dual metal CMOS technology. These high-speed, low-power
registers are ideal for use as buffer registers for data synchronization and
storage. The Output Enable (xOE) and clock (xCLK) controls are organized to
operate each device as two 8-bit registers or one 16-bit register with common
clock. Flow-through organization of signal pins simplifies layout. All inputs are
designed with hysteresis for improved noise margin.
The FCT162374T has balanced output drive with current limiting resistors.
This offers low ground bounce, minimal undershoot, and controlled output fall
times–reducing the need for external series terminating resistors.The
FCT162374T are plug-in replacements for the FCT16374T and ABT16374 for
on-board bus interface applications.
FUNCTIONAL BLOCK DIAGRAM
1
OE
2
OE
1
CLK
2
CLK
1
D
1
D
1
O
1
2
D
1
D
2
O
1
C
C
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2006 Integrated Device Technology, Inc.
JUNE 2006
DSC-5453/6
IDT74FCT162374AT/CT/ET
FAST CMOS 16-BIT REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
OE
1
O
1
1
O
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
–0.5 to 7
–0.5 to V
CC
+0.5
–65 to +150
–60 to 120
Unit
V
V
°C
mA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
CLK
1
D
1
1
D
2
V
TERM
(2)
Terminal Voltage with Respect to GND
V
TERM
(3)
Terminal Voltage with Respect to GND
T
STG
I
OUT
Storage Temperature
DC Output Current
GND
1
O
3
1
O
4
GND
1
D
3
1
D
4
V
CC
1
O
5
1
O
6
V
CC
1
D
5
1
D
6
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals terminals for FCT162XXX.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max.
6
8
Unit
pF
pF
GND
1
O
7
1
O
8
2
O
1
2
O
2
GND
1
D
7
1
D
8
2
D
1
2
D
2
NOTE:
1. This parameter is measured at characterization but not tested.
GND
2
O
3
2
O
4
GND
2
D
3
2
D
4
PIN DESCRIPTION
Pin Names
xDx
xCLK
xOx
xOE
Data Inputs
Clock Inputs
3-State Outputs
3-State Outputs Enable Input (Active LOW)
Description
V
CC
2
O
5
2
O
6
V
CC
2
D
5
2
D
6
GND
2
O
7
2
O
8
2
OE
GND
2
D
7
2
D
8
2
CLK
FUNCTION TABLE
(1)
Inputs
Function
Hi-Z
xDx
X
X
Load
L
H
L
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑
= LOW-to-HIGH transition
Outputs
xOE
H
H
L
L
H
H
xCLK
L
H
↑
↑
↑
↑
xOx
Z
Z
L
H
Z
Z
SSOP/ TSSOP
TOP VIEW
Register
2
IDT74FCT162374AT/CT/ET
FAST CMOS 16-BIT REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
(5)
Input HIGH Current (I/O pins)
(5)
I
IL
Input LOW Current (Input pins)
(5)
Input LOW Current (I/O pins)
(5)
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
High Impedance Output Current
(3-State Output pins)
(5)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
V
I
= GND
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
Min.
2
—
—
—
—
—
—
—
—
–80
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
–0.7
–140
100
5
Max.
—
0.8
±1
±1
±1
±1
±1
±1
–1.2
–250
—
500
V
mA
mV
µA
µA
µA
Unit
V
V
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V
,
V
IN =
V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= 5V
,
V
IN =
V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= Min
I
OH
= –24mA
V
IN
= V
IH
or V
IL
V
CC
= Min
I
OL
= 24mA
V
IN
= V
IH
or V
IL
Min
60
–60
2.4
—
Typ.
(2)
115
–115
3.3
0.3
Max.
200
–200
—
0.55
Unit
mA
mA
V
V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ±5µA at T
A
= –55°C.
3
IDT74FCT162374AT/CT/ET
FAST CMOS 16-BIT REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
ΔI
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
xOE = GND
One Input Togging
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
xOE = GND
fi = 5MHz
50% Duty Cycle
One Bit Toggling
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
xOE = GND
Sixteen BitsTogging
fi = 2.5MHz
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
60
Max.
1.5
100
Unit
mA
µA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
0.6
1.5
mA
—
1.1
3
V
IN
= V
CC
V
IN
= GND
—
3
5.5
(5)
V
IN
= 3.4V
V
IN
= GND
—
7.5
19
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
ΔI
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
ΔI
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT162374AT/CT/ET
FAST CMOS 16-BIT REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
t
SK(o)
Parameter
Propagation Delay
xCLK to xOx
Output Enable Time
Output Disable Time
Set-up Time HIGH or LOW, xDx to xCLK
Hold Time HIGH or LOW, xDx to xCLK
xCLK Pulse Width HIGH or LOW
Output Skew
(3)
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
74FCT162374AT
Min.
(2)
Max.
2
6.5
1.5
1.5
2
1.5
5
—
6.5
5.5
—
—
—
0.5
74FCT162374CT
Min.
(2)
Max.
2
5.2
1.5
1.5
2
1.5
5
—
5.5
5
—
—
—
0.5
74FCT162374ET
Min.
(2)
Max.
1.5
3.7
1.5
1.5
1.5
0
3
(4)
—
4.4
3.6
—
—
—
0.5
Unit
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
