IDT74ALVCF162835A
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
• CMOS power levels (0.4μ W typ. static)
μ
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP and TVSOP packages
IDT74ALVCF162835A
DESCRIPTION:
This 18-bit universal bus driver is built using advanced dual metal CMOS
technology. Data flow from A to Y is controlled by the output-enable (OE)
input. The device operates in the transparent mode when the latch-enable
(LE) input is high. The A data is latched if the clock (CLK) input is held at
a high or low logic level. If LE is low, the A data is stored in the latch flip-flop
on the low-to-high transition of CLK. When
OE
is high, the outputs are in the
high-impedance state.
The ALVCF162835A has series resistors in the device output structure
which will reduce switching noise in 128MB and 256MB SDRAM modules.
Designed with a drive capability of ±18mA, the ALVCF162835A is a mid-
way drive between the ALVC162835 (±12mA) and ALVC16835 (±24mA).
The ALVCF162835A is a faster version of the ALVCF162835 or
ALVC162835. It is suitable for PC133 applications and particularly SDRAM
Modules clocked at 133 MHz.
DRIVE FEATURES:
• Balanced Output Drivers: ±18mA
• Low switching noise
APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations
FUNCTIONAL BLOCK DIAGRAM
OE
CLK
LE
A
1
27
30
28
54
1
D
3
C
1
CLK
Y
1
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2008 Integrated Device Technology, Inc.
NOVEMBER 2008
DSC-4920/5
IDT74ALVCF162835A
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
NC
NC
Y
1
GND
Y
2
Y
3
V
CC
Y
4
Y
5
Y
6
GND
Y
7
Y
8
Y
9
Y
10
Y
11
Y
12
GND
Y
13
Y
14
Y
15
V
CC
Y
16
Y
17
GND
Y
18
OE
LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
NC
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
CLK
GND
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
–0.5 to +4.6
–0.5 to V
CC
+0.5
–65 to +150
–50 to +50
±50
–50
±100
Unit
V
V
°C
mA
mA
mA
mA
V
TERM
(2)
Terminal Voltage with Respect to GND
V
TERM
(3)
Terminal Voltage with Respect to GND
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
> V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Min.
4
—
—
Typ.
5
7
7
Max.
6
9
9
Unit
pF
pF
pF
NOTE:
1. As applicable to the device type.
FUNCTION TABLE
(1)
Inputs
OE
H
L
L
L
L
L
L
LE
X
H
H
L
L
L
L
CLK
X
X
X
↑
↑
H
L
Ax
X
L
H
L
H
X
X
Outputs
Yx
Z
L
H
L
H
Y
0
Y
0
(2)
(3)
TSSOP/ TVSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
OE
CLK
LE
Ax
Yx
Description
3-State Output Enable Inputs (Active LOW)
Register Input Clock
Latch Enable (Transparent HIGH)
Data Inputs
3-State Outputs
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑
= LOW-to-HIGH Transition
2. Output level before indicated steady-state input conditions were established, pro-
vided that CLK is HIGH before LE went LOW.
3. Output level before the indicated steady-state input conditions were established.
2
IDT74ALVCF162835A
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
Parameter
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
ΔI
CC
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
–0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
±10
±10
–1.2
—
40
V
mV
µA
µA
µA
µA
V
Unit
V
Quiescent Power Supply Current
Variation
—
—
750
µA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 8mA
I
OH
= – 6mA
I
OH
= – 12mA
I
OH
= – 8mA
I
OH
= – 18mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 8mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 8mA
I
OL
= 18mA
Min.
V
CC
– 0.2
1.9
1.7
2.2
2
2.4
2
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
3
IDT74ALVCF162835A
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance Outputs enabled
Power Dissipation Capacitance Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
30
12.5
V
CC
= 3.3V ± 0.3V
Typical
35
14
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
f
CLOCK
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
W
t
W
t
SU
t
SU
t
SU
t
H
t
H
t
SK(O)
Propagation Delay
Ax to Yx
Propagation Delay
LE to Yx
Propagation Delay
CLK to Yx
Output Enable Time
OE
to Yx
Output Disable Time
OE
to Yx
Pulse Duration, LE HIGH
Pulse Duration, CLK HIGH or LOW
Set-up Time, data before CLK↑
Set-up Time, data before LE↓, CLK HIGH
Set-up Time, data before LE↓, CLK LOW
Hold Time, data after CLK↑
Hold Time, data after LE↓, CLK HIGH or LOW
Output Skew
(2)
3.3
3.3
1.8
1.9
1.3
0.6
1.4
—
—
—
—
—
—
—
—
—
3.3
3.3
1.5
1.6
1.1
0.6
1.7
—
—
—
—
—
—
—
—
—
3.3
3.3
1
1.5
1
0.6
1.4
—
—
—
—
—
—
—
—
500
ns
ns
ns
ns
ns
ns
ns
ps
1
4.7
—
4.6
1.3
4.2
ns
1.4
5.9
—
6
1.1
5
ns
1.4
5.9
—
5.6
1.4
3.5
ns
1.3
5.5
—
5.4
1.3
4.6
ns
Parameter
Min.
150
1
Max.
—
4
V
CC
= 2.7V
Min.
150
—
Max.
—
4.6
V
CC
= 3.3V ± 0.3V
Min.
150
1
Max.
—
3.5
Unit
MHz
ns
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS FROM 0°C TO 65°C, C
L
= 50pF
V
CC
= 3.3V ± 0.15V
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
CLK to xYx
Min.
1.8
Max.
3.5
Unit
ns
4
IDT74ALVCF162835A
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALVC Link
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 3.3V±0.3V V
CC(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
500Ω
Pulse
Generator
(1, 2)
SAME PHASE
INPUT TRANSITION
V
CC(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
V
LOAD
Open
GND
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
6
2.7
1.5
300
300
50
t
PHL
Propagation Delay
ENABLE
CONTROL
INPUT
t
PZL
DISABLE
V
IN
D.U.T.
R
T
V
OUT
t
PLZ
V
LOAD/2
V
T
t
PHZ
V
T
0V
V
IH
V
T
0V
V
LOAD/2
V
OL
+ V
LZ
V
OL
V
OH
V
OH -
V
HZ
0V
ALVC Link
500Ω
C
L
ALVC Link
Test Circuit for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2ns; t
R
≤
2ns.
OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
t
PZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
V
LOAD
GND
Open
V
IH
V
T
0V
V
OH
V
T
V
OL
V
OH
V
T
V
OL
t
PLH2
t
PHL2
ALVC Link
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
SU
t
H
t
REM
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALVC Link
Set-up, Hold, and Release Times
INPUT
t
PLH1
t
PHL1
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
V
T
OUTPUT 1
t
SK
(x)
t
SK
(x)
V
T
ALVC Link
OUTPUT 2
Pulse Width
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
Output Skew - t
SK
(
X
)
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
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