Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC
FEATURES
2 LVCMOS Outputs
Input/Output Frequency: 1MHz to 150MHz
Supports LVCMOS or Sine Wave Input Clock
Extremely low additive Jitter
8 mA Output Drive Strength
Low Current Consumption
Single 1.8V, 2.5V, or 3.3V, ±10% Power Supply
Operating Temperature Range
o
0°C to 70°C (Commercial)
o
-40C to 85C (Industrial)
Available in DFN-6L GREEN/RoHS Compliant
Packages
DESCRIPTION
The PL133-27 is an advanced fanout buffer design for
high performance, low-power, small form-factor
applications. The PL133-27 accepts a reference
clock input of 1MHz to 150MHz and produces two
outputs of the same frequency. Reference clock
inputs may be LVCMOS or sine-wave signals (the
inputs are internally AC-coupled). PL133-27 is
designed to fit in a small 2 x 1.3 x 0.6mm DFN
package, and offers the best phase noise and jitter
performance and lowest power consumption of any
comparable IC.
PACKAGE PIN CONFIGURATION
FIN
CLK1
GND
1
2
3
6
5
4
OE
VDD
CLK0
DFN-6L
(2.0 x 1.3 x 0.6mm)
BLOCK DIAGRAM
CLK0
FIN
CLK1
OE
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 09/13/13 Page 1
PL133-27
Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC
PACKAGE PIN ASSIGNMENT
Name
FIN
CLK1
GND
CLK0
VDD
OE
Package Pin #
DFN-6L
1
2
3
4
5
6
Type
I
O
P
O
P
I
Reference clock input
Clock output
GND connection
Clock output
V
DD
connection
Output enable input
Description
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like ringing).
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply Considerations
- Place decoupling capacitors as close as possible to
the V
DD
pin(s) to limit noise from the power supply
- Multiple V
DD
pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with V
DD
can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1F for
designs using crystals < 50MHz and 0.01F for
designs using crystals > 50MHz.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
(Typical buffer impedance 20Ω)
To CMOS Input
50Ω line
Series Resistor
Use value to match output buffer impedance to
50Ω trace. Typical value 30Ω
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 09/13/13 Page 2
PL133-27
Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Storage Temperature
Ambient Operating Temperature*
SYMBOL
V
DD
V
I
V
O
T
S
MIN.
-0.5
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
UNITS
V
V
V
C
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Input (FIN) Frequency
Input (FIN) Signal Amplitude
Output Rise Time
Output Fall Time
Output to Output Skew
Duty Cycle
Input Duty Cycle is 50%
45
50
CONDITIONS
@ V
DD
= 2.5V and 3.3V
@ V
DD
= 1.8V
Internally AC coupled
15pF Load, 10/90%V
DD
, 3.3V
15pF Load, 90/10%V
DD
, 3.3V
MIN.
1MHz
0.8
2
2
TYP.
MAX.
150
65
V
DD
3
3
500
55
V
PP
ns
ns
ps
%
UNITS
MHz
DC SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
V
DD
= 3.3V, 25MHz, No Load
Supply Current, Dynamic
Operating Voltage
Output Low Voltage
Output High Voltage
Output Current
I
DD
V
DD
V
OL
V
OH
I
OSD
I
OL
= +4mA, V
DD
= 3.3V
I
OH
= -4mA, V
DD
= 3.3V
V
OL
= 0.4V, V
OH
= 2.4V,
V
DD
= 3.3V
2.4
8
V
DD
= 2.5V, 25MHz, No Load
V
DD
= 1.8V, 25MHz, No Load
1.62
MIN
TYP
1.8
1.3
0.8
3.63
0.4
MAX
UNITS
mA
mA
mA
V
V
V
mA
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 09/13/13 Page 3
PL133-27
Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC
NOISE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
V
DD
=3.3V, Frequency=26MHz
Offset=12KHz ~ 5MHz
V
DD
=3.3V, Frequency=100MHz
Offset=12KHz ~ 20MHz
MIN
TYP
130
150
MAX
UNIT
fs
fs
Additive Phase Jitter
PL133-27 Additive Phase Jitter:
VDD=3.3V, CLK=26MHz, Integration Range 12KHz to 5MHz: 0.127ps typical.
REF Input
-70
-80
-90
-100
PL133-27 Output
Phase Noise (dBc/Hz)
-110
-120
-130
-140
-150
-160
-170
10
100
1000
10000
Offset Frequency (Hz)
100000
1000000
10000000
When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the
output of the buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in
the buffer we compare the Phase Jitter numbers from the input and the output. The difference is called "Additive
Phase Jitter". The formula for the Additive Phase Jitter is as follows:
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 09/13/13 Page 4
PL133-27
Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
DFN-6L
D1
Symbol
A
A1
A3
b
e
D
E
D1
E1
L
Dimension in MM
Min.
Max.
0.45
0.60
0.00
0.05
0.152
0.152
0.15
0.25
0.40BSC
1.25
1.35
1.95
2.05
0.75
0.85
0.95
1.05
0.20
0.30
b
e
Pin 6 ID
Chamfer
E1
E
D
L
Pin1 Dot
A A1
A3
ORDERING INFORMATION (GREEN PACKAGE)
For part ordering, please contact our Sales Department:
2180 Fortune Drive, San Jose, CA 95131, USA
Tel: (408) 944-0800 Fax: (408) 474-1000
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
PL133-27 X X - R
Part Number
Package Type
G=DFN-6L
R=Tape and Reel
Temperature Range
C=Commercial (0°C to 70°C)
I=Industrial (-40°C to 85°C)
Part/Order Number
PL133-27GC-R
PL133-27GI-R
*Note: LLL designates lot number
Marking
H27
LLL
Package Option
6-Pin DFN (Tape and Reel)
Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Micrel is believed to be accurate
and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever
nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY:
Micrel’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the
President of Micrel Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
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