DATASHEET
ISL6329
Dual PWM Controller Powering AMD SVI Split-Plane Processors
The ISL6329 dual PWM controller delivers high efficiency and
tight regulation from two synchronous buck DC/DC converters.
The ISL6329 supports power control of AMD processors, which
operate from a serial VID interface (SVI). The dual output
ISL6329 features a multiphase controller to support the Core
voltage (VDD) and a single phase controller to power the
Northbridge (VDDNB).
A precision core voltage regulation system is provided by a
one-to-six-phase PWM voltage regulator (VR) controller. The
integration of two power MOSFET drivers adds flexibility in
layout and reduces the number of external components in the
multi-phase section. A single phase PWM controller with
integrated driver provides a second precision voltage
regulation system for the Northbridge portion of the processor.
This monolithic, dual controller with integrated driver solution
provides a cost and space saving power management solution.
For applications that benefit from load line programming to
reduce bulk output capacitors, the ISL6329 features temperature
compensated output voltage droop. The multiphase portion also
includes advanced control loop features for optimal transient
response to load application and removal. One of these
features is highly accurate, fully differential, continuous DCR
current sensing for load line programming and channel current
balance. Dual edge modulation is another unique feature,
allowing for quicker initial response to high di/dt load
transients.
The ISL6329 supports Power Savings Mode by dropping the
number of phases to one or two when the PSI_L bit is set. For
even greater power efficiency, diode emulation and gate
voltage optimization are implemented in PSI mode.
FN7800
Rev 0.00
April 19, 2011
Features
• Processor Core Voltage Via Integrated Multiphase Power
Conversion
• Configuration Flexibility
- 1 or 2-Phase Operation with Internal Drivers
- 3,4,5 or 6-Phase Operation with External PWM Drivers
• PSI_L Support
- Phase Shedding for Improved Efficiency at Light Load
- Diode Emulation in PSI mode
- Gate Voltage Optimization
• I
2
C Interface with 8 Selectable Addresses
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
-
0.6%
System Accuracy Over-Temperature
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing
- Temperature Compensated
• Serial VID Interface Handles up to 3.4MHz Clock Rates
• Two Level Overcurrent Protection Allows for High Current
Throttling (I
DD_SPIKE
)
• Multi-tiered Overvoltage Protection
• Selectable Switching Frequency up to 1MHz
• Simultaneous Digital Soft-Start of Both Outputs
• Pb-Free (RoHS Compliant)
FN7800 Rev 0.00
April 19, 2011
Page 1 of 38
ISL6329
Pin Configuration
ISL6329
(60 LD QFN)
TOP VIEW
PHASE_NB
47
UGATE_NB
LGATE_NB
I2C_ADDR
BOOT_NB
ISEN_NB-
ISEN_NB+
ISEN5+
ISEN4+
ISEN3+
ISEN5-
ISEN4-
ISEN3-
60
COMP_NB 1
FB_NB 2
VSEN_NB 3
DRPCTRL 4
SVC 5
SVD 6
VDDIO 7
SCL 8
SDA 9
VCC 10
RSVD 11
OFS 12
OCP 13
TCOMP1 14
TCOMP2 15
16
RGND
59
58
57
56
55
54
53
52
51
50
49
48
46
45 PWM4
44 PWM5
43 PWM6
42 PWROK
41 VDDPWRGD
40 PHASE1
39 UGATE1
61
GND
PWM3
38 BOOT1
37 LGATE1
36 GVOT
35 LGATE2
34 BOOT2
33 UGATE2
32 GND
31 EN
30
GND
PVCC
17
VSEN
18
FB_PSI
19
FB
20
COMP
21
FS
22
APA
23
ISEN6+
24
ISEN6-
25
ISEN1+
26
ISEN1-
27
ISEN2+
28
ISEN2-
29
PHASE2
Functional Pin Descriptions
PIN NAME
COMP_NB
FB_NB
VSEN_NB
DRPCTRL
PIN NUMBER
1
2
3
4
DESCRIPTION
Output of the internal error amplifier for the Northbridge regulator.
Inverting input to the internal error amplifier for the Northbridge regulator.
Non-inverting input to the Northbridge regulator precision differential remote-sense amplifier. This pin
should be connected to the remote Northbridge sense pin of the processor, VDDNB_SENSE.
Droop Control for Core and Northbridge. This pin is used to set up one of four user programmable selections
via a resistor tied to ground: Core Droop On and Northbridge Droop On; Core Droop Off and Northbridge Droop
On, Core Droop On and Northbridge Droop Off; Core Droop Off and Northbridge Droop Off.
Serial VID clock input from the AMD processor.
Serial VID data bi-directional signal to and from the master device on AMD processor.
Reference voltage for the SVI communication bus. Connect this pin to the system VDDIO and decouple
using a quality 0.1F ceramic capacitor.
Connect this pin to the clock signal for the I
2
C bus, which is a logic level input signal. The clock signal
tells the controller when data is available on the I
2
C bus.
SVC
SVD
VDDIO
SCL
5
6
7
8
FN7800 Rev 0.00
April 19, 2011
Page 5 of 38
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