FEBRUARY 2011
AS4C8M16S
128Mb/ 8M x 16 bit Synchronous DRAM (SDRAM)
Alliance Memory
Features
•
•
•
•
•
Fast access time from clock: 5/5.4 ns
Fast clock rate: 166/143 MHz
Fully synchronous operation
Internal pipelined architecture
2M word x 16-bit x 4-bank
Table1. Key Specifications
AS4C8M16S
tCK3
Clock Cycle time(min.)
tAC3
Access time from CLK(max.)
tRAS
Row Active time(min.)
tRC
Row Cycle time(min.)
Part Number
AS4C8M16S -6TCN
AS4C8M16S-6TIN
AS4C8M16S -7TCN
AS4C8M16S-7BCN
AS4C8M16S-6BIN
T: indicates TSOPII Package,
- 6/7
6/7 ns
5/5.4 ns
42/42 ns
60/63 ns
Package
TSOP II
TSOP II
TSOP II
TFBGA
TFBGA
• Programmable Mode registers
o CAS Latency: 2, or 3
o Burst Length: 1, 2, 4, 8, or full page
o Burst Type: interleaved or linear burst
o Burst stop function
Auto Refresh and Self Refresh
Operating temperature range –
o Commercial (0 ~ 70°C)
o Industrial (-40 ~ 85°C)
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V ± 0.3V power supply
Interface: LVTTL
54-pin 400 mil plastic TSOP II package
Table 2. Ordering Information
Frequency
166MHz
166MHz
143MHz
143MHz
166MHz
•
•
•
•
•
•
•
N: indicates Pb and Halogen Free for TSOPII Package
B: indicates BGA package
C:
commercial I:industrial temperatures
• 54-ball 8.0 x 8.0 x 1.2mm(max) FBGA
package
•
Pb free and Halogen free
Figure 1. Pin Assignment (Top View)
Overview
The AS4C8M16S SDRAM is a high-speed CMOS synchronous
DRAM containing 128 Mbits. It is internally configured as 4
Banks of 2M word x 16 DRAM with a synchronous interface
(all signals are registered on the positive edge of the clock
signal, CLK) . Read and write accesses to the SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration
of a BankActivate command which is then followed by a
Read or Write command.
The AS4C8M16S provides for programmable Read or
Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be
enabled to provide a self- timed row precharge that is
initiated at the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy to use.
By having a programmable mode register, the system
can choose the most suitable modes to maximize its
performance. These devices are well suited for applications
requiring high memory bandwidth and particularly well
suited to high performance PC applications.
VDD
DQ0
1
2
54
53
VSS
DQ15
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE#
CAS#
RAS#
CS#
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC/RFU
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
1
FEBRUARY 2011
AS4C8M16S
Figure 2. Block Diagram
Row
Decoder
BUFFER
CKE
2M x 16
CELL ARRAY
(BANK #A)
Column Decoder
CS#
RAS#
CAS#
WE#
DQ15
LDQM, UDQM
Row
Decoder
A10/AP
COLUMN
COUNTER
MODE
REGISTER
2M x 16
CELL ARRAY
(BANK #B)
Column Decoder
A0
A9
A11
BA0
BA1
ADDRESS
BUFFER
~
REFRESH
COUNTER
2
Row
Decoder
Row
Decoder
~
COMMAND
DECODER
DQ0
CONTROL
SIGNAL
GENERATOR
DQ Buffer
FEBRUARY 2011
AS4C8M16S
Pin Descriptions
Table 3. Pin Details of AS4C8M16S
Symbol
CLK
Type
Input
Description
Clock:
CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
Clock Enable:
CKE activates (HIGH) and deactivates (LOW) the CLK signal. If
CKE goes low synchronously with clock (set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state of
output and burst address is frozen as long as the CKE remains low. When all
banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes. CKE is synchronous except after the device enters
Power Down and Self Refresh modes, where CKE becomes asynchronous until
exiting the same mode. The input buffers, including CLK, are disabled during
Power Down and Self Refresh modes, providing low standby power.
Bank Activate:
BA0, BA1 input select the bank for operation.
BA1
0
0
1
1
A0-A11
Input
BA0
0
1
0
1
Select Bank
BANK #A
BANK #B
BANK #C
BANK #D
CKE
Input
BA0,BA1
Input
Address Inputs:
A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A8 with A10
defining Auto Precharge) to select one location out of the 2M available in the
respective bank. During a Precharge command, A10 is sampled to determine if all
banks are to be precharged (A10 = HIGH). The address inputs also provide the
op-code during a Mode Register Set command.
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
Row Address Strobe:
The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH,"
either the BankActivate command or the Precharge command is selected by the
WE# signal. When the WE# is asserted "HIGH," the BankActivate command is
selected and the bank designated by BA is turned on to the active state. When the
WE# is asserted "LOW," the Precharge command is selected and the bank
designated by BA is switched to the idle state after the precharge operation.
Column Address Strobe:
The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access
is started by asserting CAS# "LOW." Then, the Read or Write command is
selected by asserting WE# "LOW" or "HIGH."
Write Enable:
The WE# signal defines the operation commands in conjunction
with the RAS# and CAS# signals and is latched at the positive edges of CLK. The
WE# input is used to select the BankActivate or Precharge command and Read or
Write command.
CS#
Input
RAS#
Input
CAS#
Input
WE#
Input
3
FEBRUARY 2011
AS4C8M16S
LDQM,
UDQM
DQ0-DQ15
NC/RFU
V
DDQ
V
SSQ
V
DD
V
SS
Input
Input /
Output
-
Supply
Supply
Supply
Supply
Data Input/Output Mask:
Controls output buffers in read mode and masks
Input data in write mode.
Data I/O:
The DQ0-15 input and output data are synchronized with the positive
edges of CLK. The I/Os are maskable during Reads and Writes.
No Connect:
These pins should be left unconnected.
DQ Power:
Provide isolated power to DQs for improved noise immunity.
( 3.3V± 0.3V )
DQ Ground:
Provide isolated ground to DQs for improved noise immunity.
(0V)
Power Supply:
+3.3V
±
0.3V
Ground
4
FEBRUARY 2011
AS4C8M16S
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 4 shows the truth table for the operation commands.
Table 4. Truth Table (Note (1), (2))
Command State
BankActivate
BankPrecharge
PrechargeAll
Write
Write and AutoPrecharge
Read
Read and Autoprecharge
Mode Register Set
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
CKE
n-1
CKE
n
DQM BA
0,1
A
10
A
0-9,11
CS# RAS# CAS# WE#
Idle
(3)
Any
Any
Active
(3)
Active
(3)
Active
(3)
Active
(3)
Idle
Any
Active
(4)
Any
Idle
Idle
Idle
(SelfRefresh)
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
H
X
X
X
X
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
L
V
V
X
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
Row address
L
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
Column
address
(A0 ~ A8)
Column
address
(A0 ~ A8)
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
H
L
H
L
X
H
L
X
L
L
L
H
H
H
H
L
H
H
X
L
L
X
H
X
V
X
H
X
X
H
X
H
H
H
L
L
L
L
L
H
H
X
L
L
X
H
X
V
X
H
X
X
H
X
X
H
L
L
L
L
H
H
L
H
L
X
H
H
X
H
X
V
X
H
X
X
H
X
X
OP code
X
X
X
X
X
X
X
X
X
X
X
Clock Suspend Mode Entry
Active
Any
(5)
Active
Any
(PowerDown)
Power Down Mode Entry
Clock Suspend Mode Exit
Power Down Mode Exit
Data Write/Output Enable
Data Mask/Output Disable
Active
Active
H
X
H
X
X
X
X
X
Note:
1. V=Valid, X=Don't Care L=Low level H=High level
2. CKE
n
signal is input level when commands are provided.
CKE
n-1
signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode cannot enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
5
FPGA/CPLD
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