a
Tr
rm
fo
ns
CE
AN )
CT (µH
DU
IN UM
E IM
AG AX
AK M
LE
SERIES
CM7560R
CM7560
NG
TI )
RA S
T MP
EN (A
RR UM
CU XIM
MA
CE
AN )
ST S
SI HM
RE M (O
DC MU
XI
MA
2
rL
1o %
, L 25
H) ±
(µ z
L 1 kH
@
DA
SH
NU
E
MB
er
s
PC Mount Common Mode Choke
R*
Actual Size
Physical Parameters
Inches
A
0.860 ± 0.025
B
1.070 ± 0.050
C
0.830 ± 0.030
D
1.060 (Ref. only)
E
0.040 ± 0.025
F
0.025 Sq. (Typ.)
G
0.400 ± 0.010
H
0.175 ± 0.015
J
1.03 (Ref. only)
K
0.400 ± 0.010
L
0.630 + 0.010
Millimeters
21.8 ± 0.64
27.2 ± 1.27
21.1 ± 0.76
26.9 (Ref. only)
1.0 ± 0.64
0.64 Sq. (Typ.)
10.2 ± 0.3
4.4 ± 0.38
26.2 (Ref. only)
10.2 ± 0.3
16.0 ± 0.3
-563
-683
-823
-104
-124
-154
-184
-224
-274
-334
-474
-564
-684
-824
-105
-125
-155
-185
-225
-275
-335
-395
-475
-565
-685
-825
-106
-126
-156
-186
-226
-276
-336
-396
-476
-566
-686
-826
-107
-127
-157
SERIES CM7560 FERRITE CORE
56
0.013
5.5
68
0.013
5.5
82
0.013
5.5
100
0.013
5.5
120
0.015
5.5
150
0.015
5.5
180
0.019
4.5
220
0.020
4.5
270
0.025
4.5
330
0.025
3.5
470
0.030
3.5
560
0.035
3.5
680
0.040
3.5
820
0.060
2.8
1000
0.065
2.8
1200
0.095
2.2
1500
0.115
1.7
1800
0.125
1.7
2200
0.170
1.4
2700
0.180
1.4
3300
0.320
1.1
3900
0.400
1.1
4700
0.450
0.88
5600
0.500
0.88
6800
0.600
0.88
8200
0.750
0.88
10000
0.800
0.70
12000
0.900
0.70
15000
1.00
0.70
18000
1.30
0.55
22000
1.50
0.55
27000
1.80
0.44
33000
2.20
0.44
39000
2.60
0.44
47000
3.00
0.44
56000
4.00
0.35
68000
5.00
0.27
82000
5.50
0.27
100000
6.40
0.27
120000
7.80
0.22
150000
9.00
0.22
3.5
3.5
3.5
3.5
4.5
6.0
7.0
7.5
9.0
12
14
18
20
24
30
35
40
45
55
75
90
100
130
175
220
230
250
300
350
425
475
550
650
800
900
1100
1300
1800
2100
2600
3000
*Complete part # must include series # PLUS the dash #
For surface finish information, refer to www.delevanfinishes.com
Marking
DELEVAN; part number.
Example: CM7560-563
DELEVAN
CM7560-563
Packaging
Bulk only
Operating Temperature Range
–55°C to +125°C
Current Rating at 85°C Ambient
40°C Rise
Mechanical Configuration
Tape wrapped winding
sections; varnish impregnated assembly
Notes 1)
Inductance in table is for either Ll or L2.
2)
Leakage Inductance tested at Ll with L2 shorted or at L2
with Ll shorted.
3)
Windings balanced within 1%.
270 Quaker Rd., East Aurora NY 14052 • Phone 716-652-3600 • Fax 716-652-4814 • E-mail: apisales@delevan.com • www.delevan.com
1/2009
FPGA/CPLD
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