DATASHEET
ISL9208
Multi-Cell Li-ion Battery Pack OCP/Analog Front End
The ISL9208 is an overcurrent protection device and analog
front end for a microcontroller in a multi-cell Li-ion battery
pack. The ISL9208 supports battery pack configurations
consisting of 5-cells to 7-cells in series and 1 or more cells in
parallel. The ISL9208 provides integral overcurrent
protection circuitry, short circuit protection, an internal 3.3V
voltage regulator, internal cell balancing switches, cell
voltage monitor level shifters, and drive circuitry for external
FET devices for control of pack charge and discharge.
Selectable overcurrent and short circuit thresholds reside in
internal RAM registers. An external microcontroller sets the
thresholds by setting register values through an I
2
C serial
interface. Internal registers also contain the detection delays
for overcurrent and short circuit conditions.
Using an internal analog multiplexer the ISL9208 provides
monitoring of each cell voltage plus internal and external
temperature by a separate microcontroller with an A/D
converter. Software on this microcontroller implements all
battery pack control functionality, except for overcurrent and
short circuit shutdown.
FN6446
Rev.1.00
November 2, 2007
Features
• Software selectable overcurrent protection levels and
variable protect detection times
- 4 discharge overcurrent thresholds
- 4 short circuit thresholds
- 4 charge overcurrent thresholds
- 8 overcurrent delay times (Charge)
- 8 overcurrent delay times (Discharge)
- 2 short circuit delay times (Discharge)
• Automatic FET turn-off and cell balance disable on reaching
external (battery) or internal (IC) temperature limit.
• Automatic override of cell balance on reaching internal
(IC) temperature limit.
• Fast short circuit pack shutdown
• Can use current sense resistor, FET r
DS(ON)
, or Sense
FET for overcurrent detection.
• Four battery backed software controlled flags.
• Allows three different FET controls:
- Back-to-back N-Channel FETs for charge and discharge
control
- Single N-Channel discharge FET.
- Single N-Channel FET for discharge, with separate,
optional (smaller) back-to-back N-channel FETs for
charge.
• Integrated Charge/Discharge FET Drive Circuitry with
200µA (typ) turn-on current and 150mA (typ) Discharge
FET turn-off current.
• 10% Accurate 3.3V voltage regulator (minimum 25mA out
with external NPN transistor having current gain of 70).
• Monitored cell voltage output stable in 100µs.
• Internal Cell balancing FETs handle up to 200mA of
balancing current for each cell (with the number of cells
being balanced limited by the maximum package power
dissipation of 400mW).
• Simple I
2
C host interface
• Sleep operation with programmable negative edge or
positive edge wake-up.
• <10µA Sleep Mode
• Pb-free (RoHS compliant)
Applications
• Power Tools
• Battery Backup Systems
• E-Bikes
• Portable Test Equipment
• Medical Systems
• Hybrid Vehicle
• Military Electronics
Ordering Information
PART NUMBER
(Note)
ISL9208IRZ*
PART
MARKING
ISL9208 IRZ
PACKAGE
(Pb-free)
32 Ld 5x5 QFN
PKG.
DWG. #
L32.5x5B
*Add “-T” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
FN6446 Rev.1.00
November 2, 2007
Page 1 of 28
ISL9208
Pinout
ISL9208
(32 LD QFN)
TOP VIEW
TEMP3V
WKUP
RGC
SDA
RGO
NC
VC7/VCC
CB7
VCELL6
CB6
VCELL5
CB5
VCELL4
32 31 30 29 28 27 26 25
1
24
2
3
4
5
6
7
23
22
21
20
19
18
SCL
NC
NC
TEMPI
AO
VMON
CFET
DFET
CSENSE
DSENSE
DSREF
8
17
9 10 11 12 13 14 15 16
CB4
CB3
CB2
CB1
VCELL3
VCELL2
Functional Diagram
SCL SDA
VCELL1
VSS
I
2
C I/F
2
VC7/VCC
CB7
VCELL6
CB6
VCELL5
CB5
VCELL4
CB4
VCELL3
CB3
VCELL2
CB2
VCELL1
CB1
BACKUP
SUPPLY
DSREF
DSENSE
VMON
VSS
CSENSE
AO
TEMPI TEMP3V
CELL
VOLTAGES
7
LEVEL
SHIFTERS/
CELL
BALANCE
CIRCUITS
MUX
POWER
CONTROL
REGISTERS
3.3VDC
REGULATOR
CONTROL
LOGIC
OSC
TEMPERATURE
SENSOR, INT/EXT
COMPARATOR
EXT TEMP
ENABLE
WKUP
OVERCURRENT
PROTECTION
CIRCUITS
(THRESHOLD
DETECT AND
TIMING)
FET CONTROL
CIRCUITRY
RGC
RGO
DFET
FN6446 Rev.1.00
November 2, 2007
CFET
Page 2 of 28
ISL9208
Pin Descriptions
SYMBOL
VC7/VCC
VCELLN
CBN
DESCRIPTION
Battery cell 7 voltage input/VCC supply.
This pin is used to monitor the voltage of this battery cell externally at pin AO. This pin also
provides the operating voltage for the IC circuitry.
Battery cell N voltage input.
This pin is used to monitor the voltage of this battery cell externally at pin AO. VCELLN connects to the
positive terminal of CELLN and the negative terminal of CELLN + 1.
Cell balancing FET control output N.
This internal FET diverts a fraction of the current around a cell while the cell is being charged
or adds to the current pulled from a cell during discharge in order to perform a cell voltage balancing operation. This function is
generally used to reduce the voltage on an individual cell relative to other cells in the pack. The cell balancing FETs are turned on or
off by an external controller.
Ground. This pin connects to the most negative terminal in the battery string.
Discharge current sense reference.
This input provides a separate reference point for the charge and discharge current monitoring
circuits. WIth a separate reference connection, it is possible to minimize errors that result from voltage drops on the ground lead when
the load is drawing large currents. If a separate reference is not necessary, connect this pin to VSS.
Discharge current sense monitor.
This input monitors the discharge current by monitoring a voltage. It can monitor the voltage
across a sense resistor, or the voltage across the DFET, or by using a FET with a current sense pin. The voltage on this pin is measured
with reference to DSREF.
Charge current sense monitor.
This input monitors the charge current by monitoring a voltage. It can monitor the voltage across a
sense resistor, or the voltage across the CFET, or by using a FET with a current sense pin. The voltage on this pin is measured with
reference to VSS.
Discharge FET control.
The ISL9208 controls the gate of a discharge FET through this pin. The power FET is a
N-Channel device. The FET is turned on only by the microcontroller. The FET can be turned off by the microcontroller, but the ISL9208
also turns off the FET in the event of an overcurrent or short circuit condition. If the microcontroller detects an undervoltage condition
on any of the battery cells, it can turn off the discharge FET by controlling this output with a control bit.
Charge FET control.
The ISL9208 controls the gate of a charge FET through this pin. The power FET is a N-Channel device. The
FET is turned on only by the microcontroller. The FET can be turned off by the microcontroller, but the ISL9208 also turns off the FET
in the event of an overcurrent condition. If the microcontroller detects an overvoltage condition on any of the battery cells, it can turn
off the FET by controlling this output with a control bit.
Discharge load monitoring.
In the event of an overcurrent or short circuit condition, the microcontroller can enable an internal resistor
that connects between the VMON pin and VSS. When the FETs open because of an overcurrent or short circuit condition and the load
remains, the voltage at VMON will be near the VCC voltage. When the load is released, the voltage at VMON drops below a threshold
indicating that the overcurrent or short circuit condition is resolved. At this point, the LDFAIL flag is cleared and operation can resume.
Analog multiplexer output.
The analog output pin is used by an external microcontroller to monitor the cell voltages and temperature
sensor voltages. The microcontroller selects the specific voltage being applied to the output by writing to a control register.
Temperature monitor output control.
This pin outputs a voltage to be used in a divider that consists of a fixed resistor and a
thermistor. The thermistor is located in close proximity to the cells. The TEMP3V output is connected internally to the RGO voltage
through a PMOS switch only during a measurement of the temperature, otherwise the TEMP3V output is off. The TEMP3V output can
be turned on continuously with a special control bit.
Microcontroller wake up control. The TEMP3V pin is also turned on when any of the DSC, DOC, or COC bits are set. This can be used
to wake up a sleeping microcontroller to respond to overcurrent conditions with its own control mechanism.
Temperature monitor input.
This pin inputs the voltage across a thermistor to determine the temperature of the cells. When this input
drops below TEMP3V/13, an external over-temperature condition exists. The TEMPI voltage is also fed to the AO output pin through
an analog multiplexer so the temperature of the cells can be monitored by the microcontroller.
Regulated output voltage.
This pin connects to the emitter of an external NPN transistor and works in conjunction with the RGC pin
to provides a regulated 3.3V. The voltage at this pin provides feedback for the regulator and power for many of the ISL9208 internal
circuits as well as providing the 3.3V output voltage for the microcontroller and other external circuits.
Regulated output control.
This pin connects to the base of an external NPN transistor and works in conjunction with the RGO pin to
provide a regulated 3.3V. The RGC output provides the control signal for the external transistor to provide the 3.3V regulated voltage
on the RGO pin.
Wake up Voltage.
This input wakes up the part when the voltage crosses a turn-on threshold (wake up is edge triggered). The
condition of the pin is reflected in the WKUP bit (The WKUP bit is level sensitive.)
WKPOL bit = ”1”: the device wakes up on the rising edge of the WKUP pin. Also, the WKUP bit is HIGH only when the WKUP pin
voltage > threshold.
WKPOL bit = ”0”, the device wakes up on the falling edge of the WKUP pin. Also, the WKUP bit is HIGH only when the WKUP pin
voltage < threshold.
Serial Data.
This is the bidirectional data line for an I
2
C interface.
Serial Clock.
This is the clock input for an I
2
C communication link.
VSS
DSREF
DSENSE
CSENSE
DFET
CFET
VMON
AO
TEMP3V
TEMPI
RGO
RGC
WKUP
SDA
SCL
FN6446 Rev.1.00
November 2, 2007
Page 3 of 28
ISL9208
Absolute Maximum Ratings
Power Supply Voltage, VCC . . . . . . . . . .V
SS
- 0.5V to V
SS
+ 36.0V
Cell voltage, VCELL
VCELLN - (VCELLN-1), VCELL1-VSS . . . . . . . . . . . . . -0.5V to 5V
Terminal Voltage, V
TERM1
(SCL, SDA, C
SENSE
, D
SENSE
, TEMPI, RGO, AO, TEMP3V)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
- 0.5 to V
RGO
+ 0.5V
Terminal Voltage, V
TERM2
(CFET, VMON) . . . . V
SS
- 22.0V to V
CC
Terminal Voltage, V
TERM3
(WKUP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
- 0.5V to V
CC
(V
CC
<27V)
Terminal Voltage, V
TERM4
(RGC) . . . . . . . . . . . . . V
SS
- 0.5V to 5V
Terminal Voltage, V
TERM5
, (all other pins)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
- 0.5V to V
CC
+ 0.5V
Thermal Information
Thermal Resistance (Typical, Notes 1, 2)
JA
(°C/W)
JC
(°C/W)
32 Ld QFN . . . . . . . . . . . . . . . . . . . . . .
32
2
Continuous Package Power Dissipation . . . . . . . . . . . . . . . . .400mW
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 5V to 10V
Operating Voltage:
VCC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2V to 30.1V
VCELL1-VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 4.3V
VCELLN-(VCELLN-1). . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 4.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2.
JC
, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
PARAMETER
Operating Voltage
Power-Up Condition 1
Power-Up Condition 2 Threshold
SYMBOL
V
CC
V
PORVCC
V
CC
voltage (Note 3)
V
POR123
V
CELL1
- V
SS
and V
CELL2
- V
CELL1
and
V
CELL3
- V
CELL2
(rising)
(Note 3)
V
PORhys
V
CELL1
- V
SS
and V
CELL2
- V
CELL1
and
V
CELL3
- V
CELL2
(falling)
(Note 3)
V
RGO
I
RGC
I
VCC1
I
RGO1
I
VCC2
0µA < I
RGC
< 350µA
(Control current at output of RGC.
Recommend NPN with gain of 70+)
Power-up defaults, WKUP pin = 0V.
Power-up defaults, WKUP pin = 0V.
LDMONEN bit = 1, VMON floating,
CFET = 1, DFET=1, WKPOL bit = 1,
VWKUP = 10V, [AO3:AO0] bits = 03H.
LDMONEN bit = 1, VMON floating,
CFET = 1, DFET=1, WKPOL bit = 1,
VWKUP = 10V, [AO3:AO0] bits = 03H.
Default register settings, except
SLEEP bit = 1. WKUP pin = VCELL1
Default register settings, except
SLEEP bit = 1. WKUP pin = VCELL1
AO3:AO0 bits = 0000H
3.0
0.35
1.1
TEST CONDITION
MIN
9.2
4
1.7
TYP
MAX
30.1
9.2
2.3
UNIT
V
V
V
Power-Up Condition 2 Hysteresis
70
mV
3.3V Regulated Voltage
3.3VDC Voltage Regulator Control
Current Limit
V
CC
Supply Current
RGO Supply Current
V
CC
Supply Current
3.3
0.50
400
300
500
3.6
V
mA
510
410
700
µA
µA
µA
RGO Supply Current
I
RGO2
450
650
µA
V
CC
Supply Current
RGO Supply Current
VCELL Input Current (V
CELL1
)
I
VCC3
I
RGO3
I
VCELL1
10
1
14
µA
µA
µA
FN6446 Rev.1.00
November 2, 2007
Page 4 of 28
ISL9208
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
PARAMETER
VCELL Input Current (V
CELLN
)
SYMBOL
TEST CONDITION
MIN
TYP
MAX
10
UNIT
µA
I
VCELLN
AO3:AO0 bits = 0000H
OVERCURRENT/SHORT CIRCUIT PROTECTION SPECIFICATIONS
Overcurrent Detection Threshold
(Discharge) Voltage Relative To
DSREF
(Default in Boldface)
V
OCD
V
OCD
= 0.10V (OCDV1, OCDV0 = 0, 0)
V
OCD
= 0.12V (OCDV1, OCDV0 = 0,1)
V
OCD
= 0.14V (OCDV1, OCDV0 = 1,0)
V
OCD
= 0.16V (OCDV1, OCDV0 = 1,1)
Overcurrent Detection Threshold
(Charge) Voltage Relative to DSREF
(Default in Boldface)
V
OCC
V
OCC
= 0.10V (OCCV1, OCCV0 = 0, 0)
V
OCC
= 0.12V (OCCV1, OCCV0 = 0,1)
V
OCC
= 0.14V (OCCV1, OCCV0 = 1,0)
V
OCC
= 0.16V (OCCV1, OCCV0 = 1,1)
Short Current Detection Threshold
Voltage Relative to DSREF
(Default in Boldface)
V
SC
V
OC
= 0.20V (SCDV1, SCDV0 = 0, 0)
V
OC
= 0.35V (SCDV1, SCDV0 = 0,1)
V
OC
= 0.65V (SCDV1, SCDV0 = 1, 0)
V
OC
= 1.20V (SCDV1, SCDV0 = 1,1)
Load Monitor Input Threshold
(Falling Edge)
Load Monitor Input Threshold
(Hysteresis)
Load Monitor Current
Short Circuit Time-out
V
VMON
LDMONEN bit = “1”
0.08
0.10
0.12
0.14
-0.12
-0.14
-0.16
-0.18
0.15
0.30
0.60
1.10
1.1
0.10
0.12
0.14
0.16
-0.10
-0.12
-0.14
-0.16
0.20
0.35
0.65
1.20
1.45
0.25
20
Short circuit detection delay (SCLONG
bit = ‘0’)
Short circuit detection delay (SCLONG
bit = ‘1’)
Over Discharge Current Time-out
(Default In Boldface)
t
OCD
t
OCD
= 160ms (OCDT1, OCDT0 = 0, 0
and DTDIV = 0)
t
OCD
= 320ms (OCDT1, OCDT0 = 0, 1 and
DTDIV = 0)
t
OCD
= 640ms (OCDT1, OCDT0 = 1, 0 and
DTDIV = 0)
t
OCD
= 1280ms (OCDT1, OCDT0 = 1, 1
and DTDIV = 0)
t
OCD
= 2.5ms (OCDT1, OCDT0 = 0, 0 and
DTDIV = 1)
t
OCD
= 5ms (OCDT1, OCDT0 = 0, 1 and
DTDIV = 1)
t
OCD
= 10ms (OCDT1, OCDT0 = 1, 0 and
DTDIV = 1)
t
OCD
= 20ms (OCDT1, OCDT0 = 1, 1 and
DTDIV = 1)
90
5
80
160
320
640
1.25
2.5
5
10
40
190
10
160
320
640
1280
2.50
5
10
20
60
290
15
240
480
960
1920
3.75
7.5
15
30
0.12
0.14
0.16
0.18
-0.07
-0.09
-0.11
-0.13
0.25
0.40
0.70
1.30
1.8
V
V
V
V
V
V
V
V
V
V
V
V
V
mV
µA
µs
ms
ms
ms
ms
ms
ms
ms
ms
ms
V
VMONH
LDMONEN bit = “1”
I
VMON
t
SCD
FN6446 Rev.1.00
November 2, 2007
Page 5 of 28