CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
INPUT SUPPLY CURRENTS
Shutdown V
BIAS
Supply Current
DISABLE
Disable Threshold (COMP/EN pin)
OSCILLATOR
Nominal Frequency Range
I
VBIAS_S
V
DISABLE
f
OSC
f
OSC
V
BIAS
= 12V; Disabled
4
5.2
7
mA
0.375
0.4
0.425
V
ISL8105C
ISL8105I
ISL8105AC
ISL8105AI
270
240
540
510
300
300
600
600
1.5
330
330
660
660
kHz
kHz
kHz
kHz
V
P-P
Ramp Amplitude (Note 3)
POWER-ON RESET
Rising V
BIAS
Threshold
V
BIAS
POR Threshold Hysteresis
REFERENCE
Nominal Reference Voltage
Reference Voltage Tolerance
V
OSC
V
POR_R
V
POR_H
V
REF
ISL8105C (0°C to +70°C)
ISL8105I (-40°C to +85°C)
-1.0
-1.5
3.9
0.30
4.1
0.35
4.3
0.40
V
V
0.6
+1.0
+1.5
V
%
%
ERROR AMPLIFIER
DC Gain (Note 3)
Unity Gain-Bandwidth (Note 3)
Slew Rate (Note 3)
GATE DRIVERS
TGATE Source Resistance
R
TG-SRCh
V
BIAS
= 14.5V, 50mA Source Current
3.0
GAIN
DC
UGBW
SR
96
20
9
dB
MHz
V/µs
FN6306 Rev 5.00
April 15, 2010
Page 4 of 16
ISL8105, ISL8105A
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested.
(Continued)
SYMBOL
R
TG-SRCl
R
TG-SNKh
R
TG-SNKl
R
BG-SRCh
R
BG-SRCl
R
BG-SNKh
R
BG-SNKl
I
BSOC
TEST CONDITIONS
V
BIAS
= 4.25V, 50mA Source Current
V
BIAS
= 14.5V, 50mA Source Current
V
BIAS
= 4.25V, 50mA Source Current
V
BIAS
= 14.5V, 50mA Source Current
V
BIAS
= 4.25V, 50mA Source Current
V
BIAS
= 14.5V, 50mA Source Current
V
BIAS
= 4.25V, 50mA Source Current
ISL8105C; BGATE/BSOC Disabled
ISL8105I; BGATE/BSOC Disabled
NOTE:
3. Limits established by characterization and are not production tested.
19.5
18.0
MIN
TYP
3.5
2.7
2.7
2.4
2.75
2.0
2.1
MAX
UNITS
PARAMETER
TGATE Source Resistance
TGATE Sink Resistance
TGATE Sink Resistance
BGATE Source Resistance
BGATE Source Resistance
BGATE Sink Resistance
BGATE Sink Resistance
OVERCURRENT PROTECTION (OCP)
BSOC Current Source
21.5
21.5
23.5
23.5
µA
µA
Functional Pin Description (SOIC, DFN)
BOOT (SOIC Pin 1, DFN Pin 1)
This pin provides ground referenced bias voltage to the
top-side MOSFET driver. A bootstrap circuit is used to create
a voltage suitable to drive an N-Channel MOSFET (equal to
V
BIAS
minus the on-chip BOOT diode voltage drop), with
respect to LX.
VBIAS (SOIC Pin 5, DFN Pin 6)
This pin provides the bias supply for the ISL8105, as well as
the bottom-side MOSFET's gate and the BOOT voltage for
the top-side MOSFET's gate. An internal 5V regulator will
supply bias if V
BIAS
rises above 6.5V (but the BGATE/BSOC
and BOOT will still be sourced by V
BIAS
). Connect a well
decoupled +5V or +12V supply to this pin.
TGATE (SOIC Pin 2, DFN Pin 2)
Connect this pin to the gate of top-side MOSFET; it provides
the PWM-controlled gate drive. It is also monitored by the
adaptive shoot-through protection circuitry to determine
when the top-side MOSFET has turned off.
FB (SOIC Pin 6, DFN Pin 8)
This pin is the inverting input of the internal error amplifier.
Use FB, in combination with the COMP/EN pin, to
compensate the voltage-control feedback loop of the
converter. A resistor divider from the output to GND is used
to set the regulation voltage.
GND (SOIC Pin 3, DFN Pin 4)
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
COMP/EN (SOIC Pin 7, DFN Pin 9)
This is a multiplexed pin. During soft-start and normal converter
operation, this pin represents the output of the error amplifier.
Use COMP/EN, in combination with the FB pin, to compensate
the voltage-control feedback loop of the converter.
Pulling COMP/EN low (V
DISABLE
= 0.4V nominal) will
disable (shut-down) the controller, which causes the
oscillator to stop, the BGATE and TGATE outputs to be held
low, and the soft-start circuitry to re-arm. The external
pull-down device will initially need to overcome maximum of
5mA of COMP/EN output current. However, once the IC is
disabled, the COMP output will also be disabled, so only a
20µA current source will continue to draw current.
When the pull-down device is released, the COMP/EN pin
will start to rise at a rate determined by the 20µA charging up
the capacitance on the COMP/EN pin. When the COMP/EN
pin rises above the V
DISABLE
trip point, the ISL8105 will
begin a new initialization and soft-start cycle.
BGATE/BSOC (SOIC Pin 4, DFN Pin 5)
Connect this pin to the gate of the bottom-side MOSFET; it
provides the PWM-controlled gate drive (from V
BIAS
). This
pin is also monitored by the adaptive shoot-through
protection circuitry to determine when the lower MOSFET
has turned off.
During a short period of time following Power-On Reset
(POR) or shut-down release, this pin is also used to
determine the current limit threshold of the converter.
Connect a resistor (R
BSOC
) from this pin to GND. See
“Overcurrent Protection (OCP)” on page 7 for equations. An
overcurrent trip cycles the soft-start function, after two
dummy soft-start time-outs. Some of the text describing the
BGATE function may leave off the BSOC part of the name,
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