USER’S MANUAL
HI5628EVAL1
Evaluation Board
AN9840
Rev 0.00
Jul 1999
Description
The HI5628EVAL1 evaluation board provides a quick and
easy method for evaluating the HI5628IN, 125MSPS Dual 8-
Bit, DAC member. Each converter outputs a current into a
load resistor to form a voltage which can be measured by
using the included SMA connectors. The amount of current
out of the DAC is determined by an external resistor and
either an internal or external reference voltage. The
evaluation board also includes a VME digital interface that is
compatible with the HSP-EVAL board, so DDS (Direct Digital
Synthesis) can be performed with minimal setup time. A
transformer is included to take advantage of differential
signal drive.
Features
• HI5628IN, 125MSPS, Dual 8-Bit, CMOS DAC
• Simple and Easy to Use
• Standard VME/DSP Interface, HSP-EVAL Compatible
• SMA Outputs with Transformer Option
• Easily Selectable Internal or External Reference
Applications
• I and Q Signal Generation
• Modulated Carrier Generation
• General DAC Performance Evaluation
• Amplitude Modulation Via External Reference
Ordering Information
TEMP. RANGE
(
o
C)
PART NUMBER
HI5628EVAL1
25
PACKAGE
CLOCK
SPEED
Evaluation Platform 125MHz
Functional Block Diagram
P1
RSET POT
R68
DV
DD
AV
DD
T1
XFMR
IOUT
SMA5
I-CHANNEL 8 BITS
Q-CHANNEL 8 BITS
VME
64 OR 96-PIN
CLOCK
ICLK
SMA8
QCLK
SMA9
REF SELECT
AVDD
J1
EXTERNAL
REFERENCE
(OPTIONAL)
SMA7
SLEEP
J3
IOUTA
IOUTB
HI5628
U1
DAC
ICLK
QCLK
QOUTB
QOUTA
XFMR
T2
QOUT
SMA6
J2
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HI5628EVAL1
Functional Description
Overview
The evaluation board is configured to be interfaced using a
VME connector. The data input lines are tied together using
small, zero ohm resistors on the back side of the board (QD0 is
tied to ID0, continued with QD7 connected to ID7; see the
schematic, R54, 58-60, 62, 64-66). This is done so that the
data can be driven into both of the channels without having to
generate two patterns. This aids in simplifying the evaluation of
the part. If the user has the ability to generate dual patterns
during the evaluation process, these resistors must be
removed. Both series and parallel termination resistor
footprints are provided, so that the user may customize the
termination method. An internal voltage reference is available,
as well as a variable resistor for customizing the output current.
RF transformers are populated for taking advantage of the
complimentary current outputs. They can be disabled from the
circuit by removing several zero ohm resistors if a simple load
resistor output is desired.
sometimes improves with reduced output current. R35 is
provided if the user wishes to set the output current using a set
value. See the ‘Outputs’ section for more information on setting
the output current.
The footprints for SMA10 and SMA11 were provided on the
evaluation board so that separate multiplying signals could be
attached, along with alternate op amps, to overdrive the
internal reference op amps via ICOMP1 and QCOMP1 to
increase the multiplying bandwidth of the references for DACs I
and Q independently. SMA11 was placed next to prototyping
area so that an external op amp could be placed between E11
and E7, which provides access to QCOMP1 via a zero ohm
resistor, R69. It was intended that this capability also exist
between E10 and E6 for access to ICOMP1 so that it could be
driven independently if desired, but E6 was mistakenly
grounded. So the ability to overdrive ICOMP1 and QCOMP1
exists on this board, but it must be done with a single op amp
and signal simultaneously via SMA11, E7, and E11. ICOMP1
cannot be driven independently using SMA10, E6, and E10.
R56 should never be populated. See the functional block
diagram of the HI5628 in the data sheet and the evaluation
board schematic located in this document for more information.
Voltage Reference
The HI5628 has an internal voltage reference (1.16V typical)
with a
60ppm/
o
C drift coefficient over the full temperature
range of the converter. The REFLO pin (15) selects the
reference. Access to pin 15 is provided through the center pin
of Jumper J2. To enable the internal reference, it is necessary
that the jumper be placed such that pin 15 is grounded (J2 is
labeled on the board as INT and EXT, for internal and
external). The REFIO pin (23) provides access to the internal
voltage reference, or can be overdriven if the user wishes to
use an external source for the reference. Notice that a 0.1F
capacitor is placed as close as possible to the REFIO pin. This
capacitor is necessary for ensuring a quiet reference voltage.
If the user wishes to use an external reference voltage, jumper
J3 must be in place and an external voltage reference provided
via SMA7, labeled ‘EXT REF’. Jumper J2 must be changed so
that pin 16 is tied high (the supply voltage, which is the EXT
position of J2) when using an external reference. The
recommended limits of the external reference are between
15mV and 1.2V, which provides over 36dB of multiplying
capability. Performance of the converter can be expected to
decline as the reference voltage is reduced due to the
reduction in LSB current size.
If the user wishes to amplitude modulate the reference, the
REFIO pin can be overdriven with a waveform. The input
multiplying bandwidth of the REFIO input is approximately
1.4MHz. It is necessary that the multiplying signal be DC offset
so that the minimum and maximum peaks of the signal are
above 0V and less than 1.2V. The output current of each
converter is a function of the voltage reference used and the
value of R
SET
(R68 or R35 on the schematic). R68 is a
potentiometer that can be used to vary the R
SET
if the user
wishes to explore various output current levels. The board is
shipped with R68 set to ~2k. The converter’s performance
Outputs
The output current of the device is set by choosing R
SET
and
V
FSADJ
such that the resultant of the following equation is less
than 20mA:
I
OUT
= 32 x V
FSADJ
/ R
SET
.
For example, using the internal V
FSADJ
of 1.16V nominal and
an R
SET
(R35 on the schematic) value of 1.86kresults in an
I
OUT
of
approximately 20mA (maximum allowed). Choose the
output loading so that the ‘Output Voltage Compliance Range’
is not violated (-0.3 to 1.25V). If an external V
REF
is chosen, it
should not exceed +1.2V.
The output can be configured to drive a load resistor, a
transformer, an operational amplifier, or any other type of
output configuration so long as the output voltage compliance
range and the maximum output current is not violated.
Load Resistor Output
If the user wishes to use only a load resistor and no
transformer, they should remove the zero ohm resistors that
connect the outputs to the transformers. These resistors are
R51, R57, R70, and R72. See the schematic for details. The
output voltage developed is simply a function of the output
current multiplied by the output load. Care should be taken to
ensure that this voltage does not violate the output compliance
range of -300mV to 1.25V.
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HI5628EVAL1
Differential Output
The board is also configured with the following transformer
output which will result in an output voltage amplitude that is
twice that of I
OUT
x Req, where Req is the equivalent resistive
loading seen by the current outputs (~12.5 = (50//50//25).
The transformer used in this circuit is a Mini-Circuits 1:1 RF
Transformer, T1-1T. The impedance looking back into the
transformer from the 50 spectrum analyzer is 50(100/2),
so proper termination is achieved and reflections are
minimized. The transformer benefits the user by reducing the
even-order harmonics and therefore increasing the SFDR
(Spurious Free Dynamic Range). It can be taken out of the
output by removing the zero ohm jumpers, R51, 57, 70, and
72. With the transformers removed, SMAs 1-4 should be used
to measure the output voltages across the included 50loads.
HI5628
50
IOUTB (QOUTB)
100
IOUTA (QOUTA)
50
50
V
OUT
= (2 x I
OUT
x R
EQ
)V
Clock Inputs
The elaborate nature of the clock input circuit (see the schematic)
achieves versatility. It provides the means to drive both channels
from a single clock via the VME connector, or to drive each with
separate clocks via SMAs 8 and 9. Notice that the 0 resistors
(R28, 29, 50 and 53) are used as jumpers to enable the different
clock sources without degrading signal integrity, or they can be
replaced by nominal value resistors if series input termination(s)
are desired on the clock(s).
Input Termination
For clock rates below 50MSPS, the method of input
termination on the data and clock lines could be open, 50, or
nominal series, depending on the current drive available from
the digital source. The performance of the converter should not
vary greatly with the termination method for these update
rates. For clock rates above 50MSPS, it may be necessary that
50 termination resistors be used on this board to achieve
optimum spectral purity. If the digital pattern source cannot
drive this load, it is recommended that 200 series resistors be
used at high clock rates. The board is shipped with 200
series resistors on the data and clock lines. Notice that the
PCB footprints are available on the board for either termination
technique. For high clock rates, adjustment of the timing
between the clock and the data may be necessary for optimum
performance. When implementing the HI5628 onto a board
that contains the digital data/clock source in close proximity to
the DAC, it is unlikely that any termination resistors will be
required.
Note that the board is also shipped with both input channels
tied together via 0402 package resistors on the bottom of
the board. This is done so that both channels can be evaluated
from a single pattern generator. If 50 termination is used
while the channels are tied together, it should be obvious that
they are only needed on one channel, not both; else you will be
driving 25.
PIN 17 (20)
PIN 16 (21)
FIGURE 1.
Sleep
The converter can be put into ‘sleep’ mode by connecting pin 8
to either of the converter’s supply voltages. For normal
operation, it is recommended that pin 8 be tied to ground.
However, the sleep pin does have an active pulldown current,
so the pin can be left disconnected. On the evaluation board,
jumper J1 is provided for controlling the sleep pin. Remove the
jumper from J1 for normal operation and replace it for sleep
mode.
Power Supply(ies) and Ground(s)
The user can operate from either a single supply or dual
supplies. The DAC is designed to function with the digital and
analog voltages at the same value or at different values. The
DAC can be driven with a 3 or 3.3V digital supply and a 5V
analog supply. In compliance with the absolute maximum
ratings for the DAC listed in the datasheet, the digital input
voltages should not be more than DV
DD
+ 0.3V. A single power
supply wire can be attached to either DV
DD1
or AV
DD1
, and
then the DV
DD1
and AV
DD1
holes jumpered together on the
board using regular wire if a single supply is desired. The
board uses dual ground planes connected at a single point
near the converter (this is the recommended configuration).
For dual supply mode, connect a power supply wire to both
AV
DD1
and DV
DD1
and ground wires to DGND1 and AGND1
independently.
Getting Started
A summary of the external supplies, equipment, and signal
sources needed to operate the board is given below:
1. +3V to +5V power supply(ies) for HI5628.
2. Data Generator capable of generating 8-bit patterns. The
HSP-EVAL with the HSP45116 NCOM daughter board is an
option (see
‘Learning Your Way Around’).
3. Clock source (usually part of the Data Generator).
4. Spectrum Analyzer or Oscilloscope for viewing the output of
the converter.
Attach a +3V to +5V power supply to the evaluation board
connections labeled DVDD1 and AVDD1. Connect the 8 input
bits from the data generator to the evaluation board, preferably
by using a male, 64 or 96-pin VME (Versa Module Eurocard)
connector that mates with the eval board. See the schematic
for the correct pin connections. The middle row of the VME is
not used on the DAC board, which is why either a 64 or 96-pin
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Jul 1999
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HI5628EVAL1
connector will work. Connect the clock source to the eval
board, also preferably through the VME connector (or using
the clock SMAs; see the ‘Clock Inputs’ section for more
information). Failure to make clean and short connections to
the data input lines and clock source will result in a decrease in
spectral performance.
Using a coaxial cable with the proper SMA connector, attach
the output of one of the transformers, IOUT or QOUT, to the
measurement equipment that will be evaluating the converter’s
performance. Make sure that the jumpers are in their proper
placement. Consult the ‘Voltage Reference’ section and the
‘Sleep’ section of this document for a definition of the jumpers’
functionality.
the HSP evaluation kit, place the diskette into the 3.5” drive of
the PC and type:
(drive letter):\,NCOMCTRL
which will run the HSP45116 Control Panel software. Set the
control panel’s selections to the following and check one of the
outputs of the DACs at either IOUT or QOUT using the
spectrum analyzer for a frequency equal to 1.63MHz.
The clock select of the control panel should be set to ‘Osc.
CLK’. The control signals should be as follows:
0 ENPHREG
0 CLROFR
1 LOAD
0 BINFMT
1 PMSEL
The amplitude of the real output (RIN0-15) should be 8000
HEX
for full scale output. The center frequency register can be set
to 10ABCDEF
HEX
for a 1.63MHz tone. The Offset Frequency,
Phase Offset, and Time Accumulator Registers should all be
set to zeros. The spurious free dynamic range that can be
expected is typically 65dBc with this setup operating at this
frequency.
Learning Your Way Around
Direct Digital Synthesis
To ensure that everything on the board is configured properly
and functional, it is suggested that the following DDS setup be
implemented. The board test requires:
1. HI5628EVAL1 Evaluation Board.
2. Spectrum Analyzer.
3. HSP-EVAL Board with the HSP45116 NCOM Daughter
Board Attached and included software, NCOMCTRL.
4. Personal Computer (IBM compatible) with a Parallel Port.
5. 50 SMA Cable.
6. Two +5V power supplies. One for the DAC Eval Board and
one for the HSP Eval Board.
Note: If the HSP-EVAL Board is to be used, it is highly
recommended that the user obtain the User’s Manual, the data
sheet for the HSP45116 NCOM, and the User’s Manual for the
HSP45116-DB. This platform is capable of testing the
converter up to 25MSPS, which is the speed of the HSP-
EVAL’s on-board clock. The user can choose to substitute this
clock with a slower one, but the DSP chip and DSP Eval Board
are only designed to work at a maximum of 25MHz (a 52MHz
version of this DSP chip does exist but not in this evaluation
platform; see the HSP45116A). For testing of the HI5628 at
higher speeds, it is recommended that the user obtain a high
speed data generator capable of generating 8 bit patterns at
the clock speed needed. The HSP45116 NCOM generates
two, 16-bit channels of data. HI5628EVAL1 is designed so that
both of its input channels mate with both of the DSP’s output
channels. The zero ohm resistors that connect the I and Q
channels together on the DAC eval board must be removed
before using the HSP45116 evaluation board. Also, the DSP
Eval Board cannot drive 50
Comments
The HI5628EVAL1 evaluation board is prepared to evaluate
the HI5628, 8-bit Dual D/A Converter. It can be modified to
evaluate the HI5728, 10-bit Dual D/A Converter with the
inclusion of the series resistors that correspond to the 2 LSBs
of each channel and the replacement of the HI5628 with the
HI5728. The zero ohm resistors to ground on these LSBs will
also have to be removed. This allows for easier implementation
of future upgrades as the user will only have to order new D/As
and not an additional board. The HI5628 and HI5728 share
similar pinouts and their respective evaluation boards are
identical with only minor changes to the manner in which they
are populated. If the user is currently using the 8-bit device,
has more bits available digitally, and thinks they might upgrade
in the future, it is recommended that the HI5628 be
implemented into their system board with similar capabilities.
HSP-EVAL Setup for DDS
Attach the HSP-EVAL and the HSP45116 Daughter Board
together; see figure 2. Consult their respective user manuals
for details. Connect the HI5628EVAL1 board to the P2
connector of the HSP-EVAL board. Then connect these to an
IBM compatible PC via the parallel port. Provide power to both
boards. To run the software (NCOMCTRL) that accompanied
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Jul 1999
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HI5628EVAL1
HSP-EVAL/HSP45116
NCOM EVALUATION BOARD
OR A DATA GENERATOR
HI5628EVAL1
DAC MODULE
CLOCK
CIRCUIT
HI5628
HSP-EVAL/HSP45116DB
NUMERICALLY
CONTROLLED
OSCILLATOR
EVAL KIT
8 BITS
I CHANNEL
8 BITS
Q CHANNEL
PC INTERFACE
50
SMA
CABLE
+5V
POWER
SUPPLY
SOFTWARE
INCLUDED
WITH HSP-EVAL
+5V
POWER
SUPPLY
SPECTRUM ANALYZER
IBM COMPATIBLE PERSONAL COMPUTER
FIGURE 2. INTERSIL HI5628/DDS EVALUATION SYSTEM SETUP BLOCK DIAGRAM
Appendix A Description of Architecture
The segmented current source architecture has the ability to
improve the converter’s performance by reducing the amount
of current that is switching at any one time. In traditional
architectures, major transition points required the converter to
switch on or off large amounts of current. In a traditional 8-bit
R/2R ladder design, for example, the midscale transition
required equal amounts of currents switching on and off. In a
segmented current source arrangement, transitions such as
midscale become one in which you simply have an additional
intermediate current source turning on and several minor ones
turning off. In the case of the HI5628, there are 31 intermediate
current segments that represent the 5 MSBs and 3, binary-
weighted current sources representing each of the 3 LSBs.
See the Functional Block Diagram in the data sheet for a visual
representation. To relate the midscale transition example to the
HI5628, consider the following: Code 01111111 would be
represented by 15 intermediate current segments and each of
the 3 LSB current sources all turned on. To transition to code
10000000 would simply require turning off the 3 LSB current
sources and turning on the next intermediate current segment,
bringing the total amount of current switching at this ‘major’
code transition equal to the same amount switching at 30 other
code transition points in the code ramp from 0 to 255, so that
the total glitch energy is distributed more evenly.
AN9840 Rev 0.00
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