S i 3 0 0 0 P P T- E V B
E
V A L U A T I O N
B
O A R D
F
O R T H E
Si3000
W I T H T H E
P
ARALLEL
P
ORT
I
NTERFACE
Description
The Si3000PPT-EVB provides the audio system
engineer an easy way to evaluate the functionality of
Silicon Laboratories’ Si3000 voice band codec solution.
The Si3000 chipset can be easily controlled from a PC
using the supplied application software (requires
Si30xxPPT software Rev 2.1 or above and FPGA Rev
2.1 or above).
Features
The Si3000PPT-EVB includes the following:
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Ability to read and write registers
DAC waveform generation from a series of standard
waveforms or from a .wav file
ADC data capture and display in either time or
frequency domain
Recommended layout for key components
Daisy-chain support when used with Si30xx (Si3034,
Si3035, Si3044, or Si3056) products
RJ-11 Interface to Handset
RJ-11 Connection to Phone Line and Modem
Microphone, Speaker Interfaces
Line In, Line out Interfaces
Functional Block Diagram
12 V
Motherboard
Speaker
Out
Mic
In
Daughtercard
PPT
FPGA
SSI
Si3000
Line
Out
Line
In
Handset
Select
Phone Line
Handset
Line Level
Audio I/O
Rev. 0.1 10/03
Copyright © 2003 by Silicon Laboratories
Si3000PPT-EVB-01
Si3000PPT-EVB
Functional Description
The Si3000PPT-EVB provides the audio system
engineer an easy way to evaluate the Si3000 voice
band codec solution.
The Si3000PPT-EVB also supports the connection of
multiple devices on an SSI interface. The evaluation
board provides a straightforward means of evaluating
this feature.
The evaluation board consists of the Si30xxPPT-EVB
motherboard and the Si3000DC_EVB daughter card. A
custom ribbon cable is also provided to connect to the
parallel port of a PC. Contact a Silicon Laboratories
representative for more information.
In this document, the Si3000DC-EVB is occasionally
referred to as the “daughter card” and the Si30xxPPT-
EVB as the “motherboard”. The Si3000PPT-EVB refers
to the system which consists of both the “motherboard”
and “daughter card”.
Optional Call Progress Speaker
This feature is not utilized by the Si3000
Reset Circuit
The Si3000 requires an active low pulse on RESET
following powerup and whenever all registers need to
be reset. For development purposes, the Si3000PPT-
EVB includes a reset push button, SW1, that is used by
the FPGA to generate the reset pulse of the Si3000.
If multiple boards are cascaded together, the reset
signal should be generated by the master board. Using
the SW1 pushbutton on slave boards does not reset
that slave board.
Serial Modes
The Si3000 supports several different serial modes for a
glueless interface to many standard DSP and ASIC
serial ports. The serial mode of the Si3000 can be
selected by JP3 and JP4 on the motherboard.
Motherboard–Daughter Card Connection
The Si3000DC-EVB connects to the Si30xxPPT-EVB
through two sockets: JP1 and JP2. JP1 is a 3x8 socket
connection to the digital signals of the DSP-side chip. In
addition, a 3.3 V regulated supply is routed to this
socket and supplies the power to the digital-side device.
JP1 of the daughter card connects to JP2 of the
Si30xxPPT-EVB. JP2 is a 2x5 socket connection from
the TIP and RING and chassis ground of the line
interface to the line-side device. JP2 of the Si3000DC-
EVB connects to JP1 of the Si30xx PPT EVB.
Line Connection
The Si3000PPT-EVB has a physical interfaces
designed to connect to the phone line. It is on the
daughter card. These interfaces are equivalent and
interchangeable. When using the Si3000PPT-EVB in
slave mode, one of the line interfaces is used to connect
to the phone line, while the other line interface is used to
connect to the Master Board Modem Line Interface.
This way, both the Si3000PPT-EVB and Si30xxPPT-
EVB gain access to the phone line without requiring an
external phone splitter.
Power Supply
Power is supplied to the EVB by means of J3 or J4. J3
is a euroblock header that allows for connection to a
bench power supply. J4 is a 2.1 mm power jack that
allows the use of a wall transformer. A 9 V supply/
300 mA is typically used, but the onboard voltage
regulator also works with a dc voltage between 7.5 V
and 20 V. A diode bridge is used to correct polarity. The
on-board regulator, U7, provides 5 V to the call progress
circuit, the on-board oscillator, and other boards daisy
chained to the Si30xxPPT-EVB. This 5 V is further
regulated to 3.3 V to power the daughter card and the
input/output ports of the FPGA. A third regulator
provides 2.5 V for the core voltage of the FPGA.
Handset Interface
The Si3000PPT-EVB includes a handset interface. This
interface is located on the daughter card J1 connector
pins 9 and 10.
A handset can connect directly to the phone line or the
the Si3000 device. The target system is expected to
control the DPDT relay to select the handset
connection. When the handset is connected to the
Si3000, both the Si3000 and handset are disconnected
from the phone line. In this case, the Si3000PPT-EVB
supplies dc power to the handset through an external
12 Vdc bench supply. The euroblock header, J6, on the
daughter card is provided for this connection. 24.5 mA
of DC loop current is supplied to the handset.
In a voice modem application, the Si3000PPT-EVB is
configured in the slave mode, with an Si30xxPPT-EVB
acting as the master board. When this system is in the
on-hook state, either the Si30xx or the handset can
respond to the phone ring and place the system in the
off-hook state.
Clock Generation
The Si3000 requires an MCLK input. An on-board
oscillator (Y1) is used by the FPGA to clock all the
subsystems as well as generate and provide the master
clock to the Si3000. The FPGA is designed to use a
18.432 MHz oscillator (included with the board).
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Preliminary Rev. 0.1
Si3000PPT-EVB
If the system software chooses to allow the Si30xx EVB
to go off hook, the handset is excluded from the phone
loop and is connected directly to the Si3000 EVB. Voice
traffic is handled by the Si3000 and system software is
responsible for creating a virtual voice connection
between the handset and the phone system through the
Si3000 and Si30xx devices.
PC Parallel Port
JP13 connects through the Silicon Labs custom ribbon
cable to the parallel port of the PC. The parallel port
connection allows the designer to read and write the
Si3000 register using the evaluation software included
with the Si3000PPT-EVB.
Microphone Interface
A standard 3.5 mm mini-phono connector located on
the daughter card connector J2 is used to provide an
interface from an external microphone to the Si3000.
The input impedance to MIC input of the Si3000 is at
least 10 kW. The Si3000 has a programmable pre-
amplification to support many input line levels.
If Jumper JP3 on the daughter card is populated, the
microphone can be powered directly from the Si3000
MBIAS output. The MBIAS output provides a typical
voltage of 2.5 V and can supply up to 5 mA,
programmable through an external resistor. For
applications that cannot be met by the Si3000’s MBIAS
output, the jumper may be removed and an external
biasing voltage can be applied to the microphone.
Configuring the Si3000PPT-EVB
The S3000PPT-EVB is used to interface the Si3000
audio codec to a PC or other audio system for easy
evaluation. It uses an FPGA to translate the parallel port
interface to the SSI bus to communicate to the Si3000.
The audio data and control data are communicated from
the controlling PC using the aforementioned software.
This mode allows the user to evaluate the Si3000
without any lab equipment other than a PC.
When in mode 0, the negative edge of FSYNC indicates
the starting of the frame, and FSYNC is low until the end
of data transfer. By selecting mode 1 operation, the
rising edge of FSYNC indicates the start of the frame
but is only high for one cycle. To evaluate the Si3000’s
multiple device operation, chain the slave boards with
JP3 and JP4 on the moterboard to set to Mode 2. See
Table 1 for a description of these operating modes.
Speaker Interface
A standard 3.5 mm mini-phone connector is located on
the daughter card connector J3. The Si3000 SPKRR
and SPKRL outputs are designed to drive 60 W loads
directly. To drive a 32 W headset, an external series
resistor (30 W) is needed. Driving a 32 W headset
directly may result in reduced THD and Dynamic Range
performance. The maximum voltage swing is 1 Vrms for
either the left or right speaker drivers. The Si3000
speaker
outputs
have
programmable
analog
attenuation.
Table 1. Mode Configuration
Mode
0
1
2
3
M1
0
0
1
1
M2
0
1
0
1
Description
FSYNC frames data
FSYNC pulse starts data frame
Slave mode
Reserved
Line Input Interface
A standard RCA jack on the daughter card connector J5
is used to provide the line-level audio inputs to the
Si3000. The Si3000 has a programmable pre-amplifier.
The input impedance of the LINEI is at least 10 kΩ. The
Si3000 supports multiple levels of pre-amplification to
support various line-levels.
The evaluation board has the ability to interface in two
different modes of the SSI bus: 5-bit address space
operation is used for the Si3000/34/35/44, and 7-bit
address space operation is used for the Si3056. The on-
board FPGA will auto-detect the chip and set the
appropreate registers.
Line Output Interface
A standard RCA jack on the daughter card connector J4
is used to provide the line-level audio outputs from the
Si3000. The Si3000 line output gain is programmable.
The maximum output voltage is 1 Vrms.
Preliminary Rev. 0.1
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Si3000PPT-EVB
Evaluation Software
The Si3000PPT-EVB includes an easy-to-use graphical
interface for controlling the evaluation platform. The
software is called Si30xxPPT evaluation software. This
software allows the system designer to characterize the
Si3000 voice band codec performance without
constructing any custom hardware. The evaluation
software includes the following features:
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Run:
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Exit: Stops the program
Save: Stores the audio waveform into .wav files
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Configure:
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Configure Device: Display hardware status and user
configuration. User can set advanced software options.
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Reset Device: Resets device and executes basic
initialization sequences.
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Design Tool
Register Map: Displays register map of the device
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Signal Flow Diagram: Displays signal flow diagram of
the device.
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Transhybrid Loss Calculation: Calculate transhybrid loss
over frequency
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Ringing: Helps user program ring validation registers.
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Ability to read and write the Si3000 registers using
the SSI bus
DAC waveform generation from a series of standard
waveforms or from a .wav file
ADC data capture and display in either time or
frequency domain using the SSI bus
Daisy-chain support
Transmit and receive path attenuation and gain
settings
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Help: Displays information about the evaluation
board
PC System Requirements
The application software for the Si30xxPPT-EVB has
the following system requirements:
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Windows98 or Windows2000
Available parallel port
EPP or ECP parallel port mode for Windows 98
EPP parallel port mode for Windows 2000
450 MHz Pentium II or greater recommended
64 MB of memory or greater recommended
Installation
The supplied CD contains the Si30xxPPT-EVB windows
driver files as well as a setup utility for installing the
evaluation software.
To install the Si30xxPPT-EVB software, run the
installation program on the “Silicon Laboratories
Wireline Software CD.” The path for the installation
program is Si30xx Evaluation Software\setup.exe. The
installer guides the user through the installation process
for Si30xxPPT-EVB.exe and the LabVIEW Run-Time
engine.
Using the Si3000PPT-EVB
Application Software
A shortcut for starting the application software that
controls the Si3000PPT-EVB is installed in the Windows
Start Menu under the Programs folder in the “Si30xx
Evaluation Software” folder.
Application Menus
Three pulldown menus are used to configure the
operation of the software:
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Preliminary Rev. 0.1
Si3000PPT-EVB
Figure 1. Si30xxPPT-EVB Evaluation Software in the Audio Data Monitoring View
Audio Data Monitoring View
The audio data monitoring view is discussed in the
following sections.
Receive Audio Data of Channel#
Allows selection of channel to control and view. The
Audio Data Monitoring view allows the generation of
DAC data and the capture and display of ADC data.
Operation of the front panel in Line Monitoring view is
detailed in the following list. See Figure 1.
TX Control
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DAC Waveform: Selects the waveform to be
generated by the DAC. The waveform types are as
follows: dc, Sine, Square, Ramp, and .wav file.
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TX Gain (dB): Selects the transmit path gain/
attenuation.
TX Mute: This function is not availabe on the
Si3000PPT-EVB
Sampling Rate: This function is not availabe on the
Si3000PPT-EVB
Amplitude: Sets the amplitude of the DAC waveform
in either volts or the units of DAC codes. The units
are determined by the Amplitude Units control.
Frequency: Selects the frequency (Hz) of the
waveform to generate. The actual waveform
frequency may vary slightly from the entered value.
This variation is due to the requirement to fit an
integer number of samples into the transmit buffer.
The control is updated to reflect the actual waveform
frequency generated. The equation for calculating
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Preliminary Rev. 0.1
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