Frequency stability: ±25 ppm, ±50 ppm and ±100 ppm
(Spread = OFF)
Operating voltage: 1.8V or 2.5 or 3.3 V; other voltages up to 3.63 V
(contact SiTime)
Operating temperature range: Industrial, -40°C to +85°C, Extended
Commercial, -20°C to +70°C
Industry-standard packages: 2.5 x 2.0, 3.2 x 2.5, 5.0 x 3.2,
7.0 x 5.0 mm x mm
Pb-free, RoHS and REACH compliant
High drive option: 30pF load (contact factory)
30 ps Ultra-low cycle-to-cycle jitter
Set-top boxes and LCD displays
Scanners, printers and copiers
Interface controllers and graphics cards
PCI, CPU and memory buses
Routers and modems
DC Electrical Characteristics
Parameters
Output Voltage High
Output Voltage Low
Input Voltage High
Input Voltage Low
Operating Current
Standby Current
Power Up Time
Symbol
VOH
VOL
VIH
VIL
Idd
I_std
Min.
90
–
70
–
–
–
–
–
Typ.
–
–
–
–
–
–
30
–
Max.
–
10
–
30
27
34
50
10
Unit
%Vdd
%Vdd
%Vdd
%Vdd
mA
mA
µA
ms
IOH = -9 mA
IOL = 9 mA
Pin 1
Pin 1
Output frequency = 30 MHz, 15 pF load
Output frequency = 125 MHz, 15 pF load
Output is weakly pulled down, ST = GND
Time from minimum power supply voltage to the first cycle
(Guaranteed no runt pulses)
IOH = -7 mA
IOL = 7 mA
Pin 1
Pin 1
Output frequency = 30 MHz, 15 pF load
Output frequency = 125 MHz, 15 pF load
Output is weakly pulled down, ST = GND
Time from minimum power supply voltage to the first cycle
(Guaranteed no runt pulses)
IOH = -5 mA
IOL = 5mA
Pin 1
Pin 1
Output frequency = 30 MHz, 15 pF load
Output frequency = 125 MHz, 15 pF load
Output is weakly pulled down, ST = GND
Time from minimum power supply voltage to the first cycle
(Guaranteed no runt pulses)
Condition
Vdd = 3.3V ±10%, -40°C to 85°C
Vdd = 2.5V ±10%, -40°C to 85°C
Output Voltage High
Output Voltage Low
Input Voltage High
Input Voltage Low
Operating Current
Standby Current
Power Up Time
VOH
VOL
VIH
VIL
Idd
I_std
90
–
70
–
–
–
–
–
–
–
–
–
–
–
30
–
–
10
–
30
26
31
50
10
%Vdd
%Vdd
%Vdd
%Vdd
mA
mA
µA
ms
Vdd = 1.8V ±5%, -40°C to 85°C
Output Voltage High
Output Voltage Low
Input Voltage High
Input Voltage Low
Operating Current
Standby Current
Power Up Time
VOH
VOL
VIH
VIL
Idd
I_std
90
–
70
–
–
–
–
–
–
–
–
–
–
–
30
–
–
10
–
30
26
31
50
10
%Vdd
%Vdd
%Vdd
%Vdd
mA
mA
µA
ms
SiTime Corporation
Rev. 1.2
990 Almanor Avenue
Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised September 17, 2014
SiT9001
High Performance Spread Spectrum Oscillator
The Smart Timing Choice
The Smart Timing Choice
AC Electrical Characteristics
Parameters
Clock Output Frequency
Clock Output Duty Cycle
Clock Output Rise Time
Clock Output Fall Time
Cycle-to-cycle Jitter
Symbol
Fout
DC
tr
tf
Tccj
Min.
1
45
40
–
–
–
–
Typ.
–
50
–
1.0
1.0
22
22
Max.
200
55
60
1.5
1.5
29
29
Unit
MHz
%
%
ns
ns
ps
ps
Output frequency = 1 MHz to 75 MHz
Output frequency = 75 MHz to 200 MHz
15 pF Load, 20% to 80% Vdd
15 pF Load, 80% to 20% Vdd
Spread = OFF, Output frequency = 133.33 MHz
Spread = ON, Output frequency = 133.33 MHz
2% down spread
Condition
Vdd = 3.3V ±10%, -40°C to 85°C
Vdd = 2.5V ±10%, -40°C to 85°C
Clock Output Frequency
Clock Output Duty Cycle
Clock Output Rise Time
Clock Output Fall Time
Cycle-to-cycle Jitter
Fout
DC
tr
tf
Tccj
1
45
40
–
–
–
–
–
50
–
1.0
1.0
26
26
200
55
60
1.5
1.5
37
37
MHz
%
%
ns
ns
ps
ps
Output frequency = 1 MHz to 125 MHz
Output frequency = 125 MHz to 200 MHz
15 pF Load, 20% to 80% Vdd
15 pF Load, 80% to 20% Vdd
Spread = OFF, Output frequency = 133.33 MHz
Spread = ON, Output frequency = 133.33 MHz
2% down spread
Vdd = 1.8V ±5%, -40°C to 85°C
Clock Output Frequency
Clock Output Duty Cycle
Clock Output Rise Time
Clock Output Fall Time
Cycle-to-cycle Jitter
Fout
DC
tr
tf
Tccj
1
45
40
–
–
–
–
–
50
–
1.0
1.0
45
45
200
55
60
1.5
1.5
57
57
MHz
%
%
ns
ns
ps
ps
Output frequency = 1 MHz to 75 MHz
Output frequency = 75 MHz to 200 MHz
15 pF Load, 20% to 80% Vdd
15 pF Load, 80% to 20% Vdd
Spread = OFF, Output frequency = 133.33 MHz
Spread = ON, Output frequency = 133.33 MHz
2% down spread
Pin Configuration
Pin
Symbol
Standby
1
ST/OE/SD
Output Enable
SD (Down Spread)
only
2
3
4
GND
SS_OUT
VDD
Power
Output
[1]
Functionality
H or Open : specified frequency output
L: output is low (weak pull down). Oscillator stops
H or Open
[1]
: specified frequency output
L: output is high impedance.
Standby/ Output Enable/ Spread Disable.
H or Open: Spread = ON
L: Spread =OFF
Connect to Ground
1 to 200 MHz Spread Spectrum Clock Output
Connect to 1.8V or 2.5V or 3.3V
GND
2
3
SS_OUT
ST/OE/SD
1
Top View
4
VDD
Note:
1. A pull-up resistor of <10 k between ST/OE/SD pin and Vdd is recommended in high noise environment.
Block Diagram
VDD
SS_OUT
MEMS
Resonator
High
Performance
Synthesizer
Spread
Spectrum
Modulator
ST/OE/SD
GND
Rev. 1.2
Page 2 of 9
www.sitime.com
SiT9001
High Performance Spread Spectrum Oscillator
The Smart Timing Choice
The Smart Timing Choice
Absolute Maximum
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual perfor-
mance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameters
Storage Temperature
VDD
Electrostatic Discharge
Theta JA (with copper plane on VDD and GND)
Theta JC (with PCB traces of 0.010 inch to all pins)
Soldering Temperature (follow standard Pb free soldering guidelines)
Number of Program Writes
Program Retention over -40 to 125C, Process, VDD (0 to 3.65V)
Min.
-65
-0.5
–
–
–
–
–
–
Max.
150
+3.66
2000
75
24
260
1
1,000+
Unit
°C
V
V
°C/W
°C/W
°C
NA
years
Operating Conditions
Parameters
Supply Voltages,
VDD
[2]
Min.
2.97
2.25
1.7
Frequency Stability, Spread = OFF (down spread only)
(Inclusive of Initial stability, operating temperature, rated power supply voltage
change, load change, aging (1 ppm first year @ 25°C), shock and vibration)
Extended Commercial Operating Temperature
Industrial Operating Temperature
Maximum Load Capacitance
[3]
Typ.
3.3
2.5
1.8
–
–
–
–
–
Max.
3.63
2.75
1.9
+50
+100
70
85
15
Unit
V
V
V
ppm
ppm
°C
°C
pF
-50
-100
-20
-40
–
Notes:
2. The 3.3V device can operate from 2.25V to 3.63V with higher output drive strength, however, the data sheet specifications cannot be guaranteed. Please contact
factory for this option.
3. The output driver strength can be programmed to drive up to 30 pF load. Please contact factory for this option.
Thermal Considerations
Package
7050
5032
3225
2520
JA, 4 Layer Board
(°C/W)
191
97
109
117
JA, 2 Layer Board
(°C/W)
263
199
212
222
JC, Bottom
(°C/W)
30
24
27
26
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensibility Level
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Condition/Test Method
Rev. 1.2
Page 3 of 9
www.sitime.com
SiT9001
High Performance Spread Spectrum Oscillator
The Smart Timing Choice
The Smart Timing Choice
Description
The SiT9001 is a spread-spectrum capable, programmable
MEMS oscillator. The SiT9001 offers unparalleled flexibility in
terms of frequency range, frequency accuracy stability, supply
voltage, and operating temperature range while simultane-
ously offering outstanding performance in terms of low jitter
and a higher frequency range. This flexibility and high perfor-
mance is made available in packages down to 2.5 x 2.0 mm,
making the SiT9001 the smallest programmable
spread-spectrum oscillator available.
The SiT9001 is factory programmable and offers two types of
spread modulation: down spread modulation, and center
spread modulation. In down spread modulation mode, a
spread disable pin is available (Pin 1).
Power down (either output enable or standby) mode options
are available for both down spread and center spread versions
of the SiT9001.
The SiT9001, by eliminating the quartz crystal, has improved
immunity, shock, strain and humidity.
To order samples, go to
www.sitime.com
and click on Request
Sample” link.
Spread Spectrum Modes
[4]
Center Spread
Down Spread
Code
Down Spread
Code
Down Spread
1
Down Spread
4
Down Spread
2
Down Spread
5
Down Spread
3
Down Spread
6
Down Spread
Note:
4. In both modes, triangle modulation is employed with a frequency of ~32 kHz.
.
Down Spread: -2%
Down Spread: -1%
Down Spread: -0.5%
The SiT9001 can be factory programmed to provide down spread modulation or center spread modulation. In the down spread
modulation mode, pin 1 can be factory programmed as a spread disable pin. In both the down spread and center spread
modulation modes, pin can be factory programmed to be either output enable or standby.
Rev. 1.2
Page 4 of 9
www.sitime.com
SiT9001
High Performance Spread Spectrum Oscillator
The Smart Timing Choice
The Smart Timing Choice
Programmable Drive Strength
The SiT9001 includes a programmable drive strength feature
to provide a simple, flexible tool to optimize the clock rise/fall
time for specific applications. Benefits from the programmable
drive strength feature are:
• Improves system radiated electromagnetic interference
(EMI) by slowing down the clock rise/fall time
• Improves the downstream clock receiver’s (RX) jitter by de-
creasing (speeding up) the clock rise/fall time.
• Ability to drive large capacitive loads while maintaining full
swing with sharp edge rates.
For more detailed information about rise/fall time control and
drive strength selection, see the SiTime Applications Note
section;
http://www.sitime.com/support/application-notes.
EMI Reduction by Slowing Rise/Fall Time
Figure 1 shows the harmonic power reduction as the rise/fall
times are increased (slowed down). The rise/fall times are
expressed as a ratio of the clock period. For the ratio of 0.05,
the signal is very close to a square wave. For the ratio of 0.45,
the rise/fall times are very close to near-triangular waveform.
These results, for example, show that the 11th clock harmonic
can be reduced by 35 dB if the rise/fall edge is increased from
5% of the period to 45% of the period.
10
0
trise=0.05
trise=0.1
trise=0.15
trise=0.2
trise=0.25
trise=0.3
trise=0.35
trise=0.4
trise=0.45
strength, the rise/fall time becomes slower as the output load
increases. As an example, for a 3.3V SiT9001 device with
default drive strength setting, the typical rise/fall time is 1ns for
15 pF output load. The typical rise/fall time slows down to
2.6ns when the output load increases to 45 pF. One can
choose to speed up the rise/fall time to 1.68ns by then
increasing the drive strength setting on the SiT9001.
The SiT9001 can support up to 60 pF or higher in maximum
capacitive loads with up to 3 additional drive strength settings.
Refer to the
Drive Strength Settings Table
to determine the
proper drive strength for the desired combination of output
load vs. rise/fall time
SiT9001 Drive Strength Selection
The Drive Strength Settings Table define the rise/fall time for
a given capacitive load and supply voltage.
1. Select the table that matches the SiT9001 nominal supply
voltage (1.8V, 2.5V, 2.8V, 3.0V, 3.3V).
2. Select the capacitive load column that matches the appli-
cation requirement (5 pF to 60 pF)
3. Under the capacitive load column, select the desired
rise/fall times.
4. The left-most column represents the part number code for
the corresponding drive strength.
5. Add the drive strength code to the part number for ordering
purposes.
Calculating Maximum Frequency
Based on the rise and fall time data given in Tables 1 through
4, the maximum frequency the oscillator can operate with
guaranteed full swing of the output voltage over temperature
as follows:
M a x F re q u e n c y =
1
5 x T rf_ 2 0 /8 0
Harmonic amplitude (dB)
-10
-20
-30
-40
-50
-60
-70
-80
1
3
5
7
9
11
Harm onic num ber
Figure 1. Harmonic EMI reduction as a Function of
Slower Rise/Fall Time
Jitter Reduction with Faster Rise/Fall Time
Power supply noise can be a source of jitter for the
downstream chipset. One way to reduce this jitter is to
increase rise/fall time (edge rate) of the input clock. Some
chipsets would require faster rise/fall time in order to reduce
their sensitivity to this type of jitter. The SiT9001 provides up
to 3 additional high drive strength settings for very fast rise/fall
time. Refer to the
Drive Strength Settings Table
to determine
the proper drive strength.
High Output Load Capability
The rise/fall time of the input clock varies as a function of the
actual capacitive load the clock drives. At any given drive
Where Trf_20/80 is the typical rise/fall time at 20% to 80%
Vdd
Example 1
Calculate f
MAX
for the following condition:
• Vdd = 1.8V
• Capacitive Load: 30 pF
• Desired Tr/f time = 3 ns (rise/fall time part number code = E)
Part number for the above example:
SiT9001AIE14-33E6-123.12345
Drive strength code is inserted here. Default setting is “-”
Internal tri-state signals are not recommended for FPGAs because the device architecture does not include internal tri-state logic. If designs do use internal tri-states in a flat ......
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