AR0330CM
1/3‐inch CMOS
Digital Image Sensor
Description
The AR0330 from ON Semiconductor is a 1/3-inch CMOS digital
image sensor with an active-pixel array of 2304 (H)
×
1536 (V). It can
support 3.15 Mp (2048 (H)
×
1536 (V)) digital still image capture and
a 1080p60 + 20% EIS (2304 (H)
×
1296 (V)) digital video mode. It
incorporates sophisticated on-chip camera functions such as
windowing, mirroring, column and row sub-sampling modes, and
snapshot modes.
Table 1. KEY PERFORMANCE PARAMETERS
Parameter
Optical Format
Typical Value
1/3-inch (6.0 mm)
Entire Array: 6.09 mm
Still Image: 5.63 mm (4:3)
HD Image: 5.82 mm (16:9)
2304 (H)
×
1536 (V): (Entire Array)
5.07mm (H)
×
3.38mm (V)
2048 (H)
×
1536 (V) (4:3, Still Mode)
2304 (H)
×
1296 (V) (16:9, HD Mode)
2.2
×
2.2
mm
RGB Bayer
ERS and GRR
6–27 MHz
196 Mp/s (4-lane HiSPi or MIPI)
2304
×
1296 at 60 fps
< 450 mW (V
CM
0.2 V, 198 MP/s)
2304
×
1296 at 30 fps
< 300 mW (V
CM
0.2 V, 98 MP/s)
2.0 V/lux−sec
39 dB
69.5 dB
1.7–1.9 V (1.8 V Nominal)
2.7–2.9 V
1.7–1.9 V (1.8 V Nominal)
0.3–0.9 V (0.4 or 0.8 V Nominal)
1.7–1.9 V (1.8 V Nominal)
1.7–1.9 V (1.8 V Nominal) or
2.4–3.1 V (2.8 V Nominal)
–30°C to + 70°C
CLCC
−
11.4 mm
×
11.4mm
CSP
−
6.28 mm
×
6.65 mm
Bare Die
www.onsemi.com
CLCC48
CASE 848AU
ODCSP64
CASE 570BH
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Active Pixels
Features
•
2.2
mm
Pixel with A−Pix
t
Technology
•
Full HD support at 60 fps
•
•
•
•
•
Pixel Size
Color Filter Array
Shutter Type
Input Clock Range
Output Clock Maximum
Output Video
−
4-lane HiSPi
Responsivity
SNR
MAX
Dynamic Range
Supply Voltage
Digital
Analog
HiSPi PHY
HiSPi I/O (SLVS)
HiSPi I/O (HiVCM)
I/O/Digital
Operating Temperature
(Junction)
−T
J
Package Options
•
•
•
•
•
(2304 (H)
×
1296 (V)) for Maximum
Video Performance
Superior Low-light Performance
3.4 Mp (3:2) and 3.15 Mp (4:3) Still Images
Support for External Mechanical Shutter
Support for External LED or Xenon Flash
Data Interfaces: Four-lane Serial High-speed
Pixel Interface (HiSPi) Differential
Signaling (SLVS), Four-lane Serial MIPI
Interface, or Parallel
On-chip Phase-locked Loop (PLL)
Oscillator
Simple Two-wire Serial Interface
Auto Black Level Calibration
12-to-10 Bit Output A−Law Compression
Slave Mode for Precise Frame-rate Control
and for Synchronizing Two Sensors
Applications
•
1080p High-definition Digital Video
Camcorder
•
Web Cameras and Video Conferencing
Cameras
•
Security
©
Semiconductor Components Industries, LLC, 2010
March, 2017
−
Rev. 18
1
Publication Order Number:
AR0330CM/D
AR0330CM
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number
AR0330CM1C00SHAA0−DP
AR0330CM1C00SHAA0−DR
AR0330CM1C00SHAA0−TP
AR0330CM1C00SHKA0−CP
AR0330CM1C00SHKA0−CR
AR0330CM1C12SHAA0−DP
AR0330CM1C12SHAA0−DR
AR0330CM1C12SHKA0−CP
AR0330CM1C12SHKA0−CR
AR0330CM1C21SHKA0−CP
AR0330CM1C21SHKA0−CR
Product Description
3 MP 1/3″ CIS
3 MP 1/3″ CIS
3 MP 1/3″ CIS
3 MP 1/3″ CIS
3 MP 1/3″ CIS
3 MP 1/3″ CIS
3 MP 1/3″ CIS
3 MP 1/3″ CIS
3 MP 1/3″ CIS
3 MP 1/3″ CIS
3 MP 1/3″ CIS
Orderable Product Attribute Description
Dry Pack with Protective Film
Dry Pack without Protective Film
Tape & Reel with Protective Film
Chip Tray with Protective Film
Chip Tray without Protective Film
Dry Pack with Protective Film
Dry Pack without Protective Film
Chip Tray with Protective Film
Chip Tray without Protective Film
Chip Tray with Protective Film
Chip Tray without Protective Film
GENERAL DESCRIPTION
The AR0330 can be operated in its default mode or
programmed for frame size, exposure, gain, and other
parameters. The default mode output is a 2304
×
1296 image
at 60 frames per second (fps). The sensor outputs 10- or
12-bit raw data, using either the parallel or serial (HiSPi,
MIPI) output ports.
FUNCTIONAL OVERVIEW
The AR0330 is a progressive-scan sensor that generates
a stream of pixel data at a constant frame rate. It uses an
on-chip, phase-locked loop (PLL) that can generate all
internal clocks from a single master input clock running
between 6 and 27 MHz. The maximum output pixel rate is
196 Mp/s using a 4-lane HiSPi or MIPI serial interface and
98 Mp/s using the parallel interface.
Test Pattern
Generator
Ext
Clock
Analog Core
PLL
Row Drivers
Timing
and
Control
Registers
Pixel
Array
Column
Amplifiers
ADC
12-bit
Digital Core
Row Noise Correction
Black Level Correction
Digital Gain
Data Pedestal
12-bit
Output Data-Path
Compression (Optional)
12-bit
12-bit
8-,
10-
or 12-bit
10- or 12-bit
Two-wire
Serial I/F
Parallel I/O:
PIXCLK, FV,
LV, D
OUT
[11:0]
MIPI I/O:
CLK P/N,
DATA[11:0] P/N
HiSPi I/O:
SLVS C P/N,
SLVS[3:0] P/N
Figure 1. Block Diagram
User interaction with the sensor is through the two-wire
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor is a 3.4 Mp active-pixel sensor array. The timing and
control circuitry sequences through the rows of the array,
resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the
pixels in the row integrate incident light. The exposure is
controlled by varying the time interval between reset and
readout. Once a row has been read, the signal from the
column is amplified in a column amplifier and then digitized
in an analog-to-digital converter (ADC). The output from
the ADC is a 12-bit value for each pixel in the array.
The ADC output passes through a digital processing signal
chain (which provides further data path corrections and
applies digital gain).
www.onsemi.com
2
AR0330CM
WORKING MODES
The AR0330 sensor working modes are specified from the
following aspect ratios:
Table 3. AVAILABLE ASPECT RATIOS IN THE AR0330 SENSOR
Aspect Ratio
3:2
4:3
16:10
16:9
Still Format #1
Still Format #2
Still Format #3
HD Format
Sensor Array Usage
2256 (H)
×
1504 (V)
2048 (H)
×
1536 (V)
2256 (H)
×
1440 (V)
2304 (H)
×
1296 (V)
The AR0330 supports the following working modes. To
operate the sensor at full speed (196 Mp/s) the sensor must
use the 4-lane HiSPi or MIPI interface. The sensor will
operate at half-speed (98 Mp/s) when using the parallel
interface.
Table 4. AVAILABLE WORKING MODES IN THE AR0330 SENSOR
Aspect
Ratio
16:9
Active
Readout
Window
2304
×
1296
Sensor
Output
Resolution
2304
×
1296
FPS
(4-lane MIPI/
HiSPi Interface)
60
30
3M Still
4:3
3:2
WVGA + EIS
WVGA + EIS
Slow-motion
VGA Video
VGA Video
Slow-motion
16:9
16:9
16:10
16:10
2048
×
1536
2256
×
1504
2304
×
1296
2304
×
1296
2256
×
1440
2256
×
1440
2048
×
1536
2256
×
1504
1152
×
648
1152
×
648
752
×
480
752
×
480
30
30
60
120
60
215
FPS
(Parallel Interface)
N/A
30
25
25
60
N/A
60
107
Mode
1080p + EIS
Subsampling
−
−
−
−
2×2
2×2
3×3
3×3
FOV
100%
100%
100%
100%
100%
100%
96%
96%
HiSPi POWER SUPPLY CONNECTIONS
The HiSPi interface requires two power supplies.
The V
DD
_HiSPi powers the digital logic while the
V
DD
_HiSPi_TX powers the output drivers. The digital logic
supply is a nominal 1.8 V and ranges from 1.7 to 1.9 V.
The HiSPi drivers can receive a supply voltage of 0.4 to
0.8 V or 1.7 to 1.9 V.
The common mode voltage is derived as half of the
V
DD
_HiSPi _TX supply. Two settings are available for the
output common mode voltage:
1. SLVS Mode:
The V
DD
_HiSPi_Tx supply must be in the range
of 0.4 to 0.8 V and the high_vcm register bit
R0x306E[9] must be set to “0”.
The output common mode voltage will be in the
range of 0.2 to 0.4 V.
2. HiVCM Mode:
The V
DD
_HiSPi_Tx supply must be in the range
of 1.7 to 1.9 V and the high_vcm register bit
R0x306E[9] must be set to “1”. The output
common mode voltage will be in the range of 0.76
to 1.07 V.
Two prior naming conventions have also been used with
the V
DD
_HiSPi and V
DD
_HiSPi_TX pins:
1. Digital logic supply was named V
DD
_SLVS while
the driver supply was named V
DD
_SLVS_TX.
2. Digital logic supply was named V
DD
_PHY while
the driver supply was named V
DD
_SLVS.
www.onsemi.com
3
AR0330CM
TYPICAL CONFIGURATIONS
Digital Digital
Core
I/O
Power
1
Power
1
HiSPi
Power
1
PLL
Power
1
Analog Analog
Power
1
Power
1
1.5 kW
3, 4
V
DD
_HiSPi_TX
V
DD
_HiSPi
V
DD
_MIPI
V
DD
_PLL
1.5 kW
3
V
DD
_IO
V
DD
V
AA
V
AA
_PIX
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
SLVS3_P
SLVS3_N
SLVSC_P
SLVSC_N
FLASH
SHUTTER
To Controller
(HiSPi-serial
Interface)
Master Clock
(6−27 MHz)
EXTCLK
OE_BAR
TRIGGER
From
Controller
S
ADDR
S
CLK
S
DATA
RESET_BAR
TEST
D
GND
GND_SLVS
A
GND
Digital
Ground
V
DD
_HiSPi_TX
V
DD
_IO
V
DD
V
DD
_HiSPi
Analog
Ground
V
DD
_PLL
V
AA
V
AA
_PIX
1.0
mF
0.1
mF
1.0
mF
0.1
mF
1.0
mF
0.1
mF
1.0
mF
0.1
mF
1.0
mF
0.1
mF
1.0
mF
0.1
mF
1.0
mF
0.1
mF
Notes:
1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 1.0
mF
and 0.1
mF
decoupling capacitors for
every power supply. If space is a concern, then priority must be given in the following order: V
AA
, V
AA
_PIX, V
DD
_PLL, V
DD
_IO, and V
DD
.
Actual values and results may vary depending on layout and design considerations.
2. To allow for space constraints, ON Semiconductor recommends having 0.1
mF
decoupling capacitor inside the module as close to the pads
as possible. In addition, place a 10
mF
capacitor for each supply off-module but close to each supply.
3. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed.
4. This pull-up resistor is not required if the controller drives a valid logic level on S
CLK
at all times.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is
minimized.
6. TEST pin should be tied to D
GND
.
7. Set High_VCM (R0x306E[9]) to 0 (default) to use the V
DD
_HiSPi_TX in the range of 0.4–0.8 V. Set High_VCM to 1 to use a range of
1.7–1.9 V.
8. The package pins or die pads used for the MIPI data and clock as well as the parallel interface must be left floating.
9. The V
DD
_MIPI package pin and sensor die pad should be connected to a 2.8 V supply as V
DD
_MIPI is tied to the V
DD
_PLL supply both
in the package routing and also within the sensor die itself.
10. If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.
11. If the TRIGGER pin or pad is not used then it should be tied to D
GND
.
12. The GND_SLVS pad must be tied to D
GND
. It is connected this way in the CLCC and CSP packages.
Figure 2. Serial 4-lane HiSPi Interface
www.onsemi.com
4
AR0330CM
Digital Digital
Core
I/O
Power
1
Power
1
PLL
Power
1
Analog Analog
Power
1
Power
1
1.5 kW
3, 4
V
DD
_MIPI
V
DD
_PLL
1.5 kW
3
V
DD
_IO
V
DD
V
AA
V
AA
_PIX
DATA1_P
DATA1_N
DATA2_P
DATA2_N
DATA3_P
DATA3_N
DATA4_P
DATA4_N
CLK_P
CLK_N
SHUTTER
FLASH
To Controller
(MIPI-serial
Interface)
Master Clock
(6−27 MHz)
EXTCLK
OE_BAR
From
Controller
TRIGGER
S
ADDR
S
CLK
S
DATA
RESET_BAR
TEST
D
GND
A
GND
Digital
Ground
V
DD
_IO
V
DD
V
DD
_PLL
V
AA
Analog
Ground
V
AA
_PIX
1.0
mF
0.1
mF
1.0
mF
0.1
mF
1.0
mF
0.1
mF
1.0
mF
0.1
mF
1.0
mF
0.1
mF
Notes:
1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 1.0
mF
and 0.1
mF
decoupling capacitors for
every power supply. If space is a concern, then priority must be given in the following order: V
AA
, V
AA
_PIX, V
DD
_PLL, V
DD
_MIPI, V
DD
_IO,
and V
DD
. Actual values and results may vary depending on layout and design considerations.
2. To allow for space constraints, ON Semiconductor recommends having 0.1
mF
decoupling capacitor inside the module as close to the pads
as possible. In addition, place a 10
mF
capacitor for each supply off-module but close to each supply.
3. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed.
4. This pull-up resistor is not required if the controller drives a valid logic level on S
CLK
at all times.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is
minimized.
6. TEST pin must be tied to D
GND
for the MIPI configuration.
7. ON Semiconductor recommends that GND_MIPI be tied to D
GND
.
8. V
DD
_MIPI is tied to V
DD
_PLL in both the CLCC and the CSP package. ON Semiconductor strongly recommends that V
DD
_MIPI must be
connected to a V
DD
_PLL in a module design since V
DD
_PLL and V
DD
_MIPI are tied together in the die.
9. The package pins or die pads used for the HiSPi data and clock as well as the parallel interface must be left floating.
10. HiSPi Power Supplies (V
DD
_HISPI and V
DD
_HISPI_TX) can be tied to ground.
11. If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.
12. If the TRIGGER pin or pad is not used then it should be tied to D
GND
.
Figure 3. Serial MIPI
www.onsemi.com
5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
