Freescale Semiconductor
Technical Data
MMA6222KEG
Rev 0, 12/2009
Digital Dual Axis Micromachined
Accelerometer
The MMA62XXKEG is a two-axis member of Freescale’s family of
SPI-compatible accelerometers. These devices incorporate digital signal
processing for filtering, trim and data formatting.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Available in
±20/20g, ±50/50g,
or
±100/100g
versions. Additional g-ranges
between 20 and 100g may be available upon request
Full-scale range is independently specified for each axis
400 Hz low-pass filter, 0.1 Hz high-pass filter, 4-pole, 16
μs
sample time,
additional filter options are available
Ratiometric analog voltage output
10-bit digital signed data output
SPI-compatible serial interface
Capture/hold input for system-wide synchronization support
3.3 or 5 V single supply operation
On-chip temperature sensor and voltage regulator
Bidirectional internal self-test
Minimal external component requirements
Pb-free 20-pin SOIC package
Qualified AEC-Q100, Rev. F Grade 2 (-40°C/ +105°C)
MMA6222KEG
MMA6255KEG
MMA621010KEG
2-AXIS
SPI-COMPATIBLE
ACCELEROMETER
KEG SUFFIX (Pb-free)
20-LEAD SOIC
CASE 475A-02
PIN CONNECTIONS
N/C
N/C
X
OUT
V
SSA
Y
OUT
CAP/HOLD
D
IN
V
PP
C
REG
CS/RESET
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
N/C
N/C
C
REGA
C
REGA
C
REF
C
REF
V
CC
V
SS
D
OUT
SCLK
Typical Applications
•
•
•
Crash Detection (Airbag)
Impact and vibration monitoring
Shock Detection
20-PIN SOIC PACKAGE
N/C: NO INTERNAL CONNECTION
ORDERING INFORMATION
Device Name
MMA6222EG
MMA6222EGR2
MMA6222KEG*
MMA6222KEGR2*
MMA6255EG
MMA6255EGR2
MMA6255KEG*
MMA6255KEGR2*
MMA621010EG
MMA621010EGR2
MMA621010KEG*
MMA621010KEGR2*
X-Axis, g-Level
20
20
20
20
50
50
50
50
100
100
100
100
Y-Axis, g-Level
20
20
20
20
50
50
50
50
100
100
100
100
Temperature Range
-40 to +105°C
-40 to +105°C
-40 to +105°C
-40 to +105°C
-40 to +105°C
-40 to +105°C
-40 to +105°C
-40 to +105°C
-40 to +105°C
-40 to +105°C
-40 to +105°C
-40 to +105°C
Package
475A-02
475A-02
475A-02
475A-02
475A-02
475A-02
475A-02
475A-02
475A-02
475A-02
475A-02
475A-02
Packaging
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
*Part number sourced from a different facility.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
V
CC
V
CC
C
REG
C
REGA
C
REF
100 nF
1
μF
1
μF
100 nF
CS
SCLK
DI
DO
CS_A
SCLK1
MOSI1
MISO1
CS_D
SCLK2
MOSI2
MISO2
CS
SCLK
DI
DO
MMA62XXKEG
V
SSA
V
SS
V
PP
/TEST
XOUT
YOUT
Main MCU
Deployment IC
ADC
Safing
Sensor(s)
Filter
/
Comparator
DEPLOY_EN1
DEPLOY_EN2
Note: If one axis of the MMA62XXKEG sensor is expected to be used as a confirmation of the other axis, Freescale
recommends that MMA62XXKEG used in conjunction with an additional sensing/safing device for each axis.
Figure 1-1 Simplified Airbag Application Diagram
1.1
INTRODUCTION
The MMA62XXKEG is intended for applications which utilize serial communications as the primary data transfer mechanism. In
addition, an analog output with lower accuracy is available.
Device serial number, acceleration range, filter characteristics and status information are available along with acceleration data
via the SPI interface. A pair of digital-to-analog converters is enabled to provide ratiometric voltage outputs in addition to the
digital acceleration value accessible via the SPI.
MMA6222KEG
2
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Freescale Semiconductor
1.2
BLOCK DIAGRAM
A block diagram illustrating the major components of the design is shown in
Figure 1-2.
V
PP
V
CC
C
REG
C
REGA
C
REGA
C
REF
C
REF
V
SS
V
SSA
CONTROL
LOGIC
SPI
D
IN
D
OUT
SCLK
CS
CAP/HOLD
VOLTAGE
REGULATOR
UNIT
PROGRAMMABLE
DATA ARRAY
REFERENCE
OSCILLATOR
PRIMARY
OSCILLATOR
CLOCK
MONITOR
INTERNAL
CLOCK
g-CELL
(Y)
SD
CONVERTER
SINC
FILTER
Y IN
CONTROL
IN
STATUS
OUT
DIGITAL
OUT
SELF-TEST
INTERFACE
TEMP.
SENSOR
TEMP
DSP
(SEE
FIGURE 1-2)
Y OUT
DAC
Y
OUT
X IN
X OUT
g-CELL
(X)
SD
CONVERTER
SINC
FILTER
DAC
X
OUT
Figure 1-2 MMA62XXKEG Block Diagram
CONTROL
IN
OFFSET
MONITOR
DSP
CONTROL
OUT
Y IN
X IN
LOW-PASS
FILTER
OFFSET,
GAIN,
LINEARITY
ADJUST
HIGH-PASS
FILTER
OUTPUT
SCALING
OUTPUT
SCALING
DIGITAL
OUT
TO Y DAC
TO X DAC
TEMP
Figure 1-3 MMA62XXKEG DSP Block Diagram
NOTE: Models of signal chain are available upon request.
MMA6222KEG
Sensors
Freescale Semiconductor
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1.3
PIN FUNCTIONS
The pinout for the MMA62XXKEG device is illustrated in
Figure 1-4.
Pin functions are described below. When self-test is active,
the output becomes more positive in both axes if ST1 is cleared, or more negative in both axes if ST1 is set, as described in
Section 3.1.1.
N/C
N/C
X
OUT
V
SSA
Y
OUT
CAP/HOLD
D
IN
V
PP
C
REG
CS/RESET
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
N/C
N/C
C
REGA
C
REGA
C
REF
C
REF
V
CC
V
SS
D
OUT
SCLK
20-PIN SOIC PACKAGE
N/C: NO INTERNAL CONNECTION
X: +1g
Y: 0g
X: 0g
Y: +1g
X: 0g
Y: -1g
TO CENTER OF
GRAVITATION FIELD
X: -1g
Y: 0g
Response to static orientation within 1g field.
Figure 1-4 MMA62XXKEG Pinout
MMA6222KEG
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Freescale Semiconductor
1.4
1.4.1
PIN FUNCTION DESCRIPTIONS
V
CC
This pin supplies power to the device. Careful printed wiring board layout and capacitor placement is critical to ensure best
performance. An external bypass capacitor between this pin and V
SS
is required, as described in
Section 1.5.
1.4.2
V
SS
V
SSA
This pin is the power supply return node for the digital circuitry on the MMA62XXKEG device.
1.4.3
This pin is the power supply return node for analog circuitry on the MMA62XXKEG device. An external bypass capacitor between
this pin and V
CC
is required, as described in
Section 1.5.
1.4.4
C
REG
This pin is connected to the internal digital circuitry power supply rail. An external filter capacitor must be connected between this
pin and V
SS
, as described in
Section 1.5.
1.4.5
C
REGA
These pins are connected in parallel to the internal analog circuitry power supply rail. One or two external filter capacitors must
be connected between these pins and V
SSA
, as described in
Section 1.5.
Two pins are provided to support redundant connection
to the printed wiring board assembly. Redundant external capacitors may be connected to these pins for maximum reliability, as
described in
Section 1.5.
1.4.6
C
REF
These pins are connected in parallel to an internal reference voltage node utilized by the analog circuitry. One or two external
filter capacitors must be connected between these pins and V
SSA
, as described shown in
Section 1.5.
Two pins are provided to
support redundant connection to the printed wiring board assembly. Redundant external capacitors may be connected to these
pins for maximum reliability, as described in
Section 1.5.
1.4.7
VPP
This pin should be tied directly to V
SS
.
1.4.8
SCLK
This input pin provides the serial clock to the SPI port. The state of this pin is also used as a qualifier for externally-controlled
reset. An internal pull-down device is connected to this pin. This input may be left unconnected unless it is desired to initiate de-
vice reset as described in
Section 1.4.9.
1.4.9
CS/RESET
This pin provides two functions. When the SPI is enabled, this pin functions as the chip select input for the SPI port. The state of
the D
IN
pin during low-to-high transitions of SCLK is latched internally and D
OUT
is enabled when CS is at a logic low level.
This pin may also be used to initiate a hardware reset. If CS is held low and SCLK is held high for 512
μs,
the internal reset signal
is asserted.
An internal pull-up device is connected to this pin.
1.4.10
D
OUT
This pin functions as the serial data output for the SPI port.
Immediately following device reset, D
OUT
is placed in a high impedance state for approximately 800
μs.
At the end of this time,
D
OUT
is driven high and a 3ms stabilization delay required by the internal circuitry begins. Reset is reported by the device so the
system can be aware of potential difficulties if unexpected resets occur.
1.4.11
D
IN
This pin functions as the serial data input to the SPI.
MMA6222KEG
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Freescale Semiconductor
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