19-1729; Rev 4; 11/08
KIT
ATION
EVALU
BLE
AVAILA
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
General Description
Features
o
Single 3.0V Operation
o
Excellent Dynamic Performance
59.5dB SNR at f
IN
= 20MHz
73dB SFDR at f
IN
= 20MHz
o
Low Power:
30mA (Normal Operation)
5µA (Shutdown Mode)
o
Fully Differential Analog Input
o
Wide 2V
P-P
Differential Input Voltage Range
o
400MHz -3dB Input Bandwidth
o
On-Chip 2.048V Precision Bandgap Reference
o
CMOS-Compatible Three-State Outputs
o
32-Pin TQFP Package
o
Evaluation Kit Available (MAX1448 EV Kit)
MAX1446
The MAX1446 10-bit, 3V analog-to-digital converter
(ADC) features a fully differential input, a pipelined 10-
stage ADC architecture with digital error correction and
wideband track and hold (T/H) incorporating a fully dif-
ferential signal path. This ADC is optimized for low-
power, high dynamic performance applications in
imaging and digital communications. The MAX1446
operates from a single 2.7V to 3.6V supply, consuming
only 90mW while delivering a 59.5dB signal-to-noise
ratio (SNR) at a 20MHz input frequency. The fully differ-
ential input stage has a 400MHz, -3dB bandwidth and
may be operated with single-ended inputs. In addition
to low operating power, the MAX1446 features a 5µA
power-down mode for idle periods.
An internal 2.048V precision bandgap reference is used
to set the ADC full-scale range. A flexible reference
structure allows the user to supply a buffered, direct or
externally derived reference for applications requiring
increased accuracy or a different input voltage range.
Lower and higher speed, pin-compatible versions of
the MAX1446 are also available. Refer to the MAX1444
data sheet for a 40Msps version, the MAX1448 data
sheet for an 80Msps version, and the MAX1449 data
sheet for a 105Msps version.
The MAX1446 has parallel, offset binary, three-state
outputs that can be operated from 1.7V to 3.3V to allow
flexible interfacing. The device is available in a 5mm x
5mm, 32-pin TQFP package and is specified over the
extended industrial (-40°C to +85°C) and automotive
(-40°C to +105°C) temperature ranges.
Ordering Information
PART
MAX1446EHJ+
MAX1446GHJ+
TEMP RANGE
-40°C to +85°C
-40°C to +105°C
PIN-
PACKAGE
32 TQFP
32 TQFP
+Denotes
a lead(Pb)-free/RoHS-compliant package.
________________________Applications
Ultrasound Imaging
CCD Imaging
Baseband and IF Digitization
Digital Set-Top Boxes
Video Digitizing Applications
IN+
T/H
IN-
CLK
Functional Diagram
MAX1446
CONTROL
V
DD
GND
PIPELINE ADC
D
E
C
10
OUTPUT
DRIVERS
D9–D0
Pin-Compatible,
Lower/Higher Speed Versions
PART
MAX1444
MAX1448
MAX1449
SAMPLING SPEED (Msps)
40
80
105
PD
REF
REF SYSTEM +
BIAS
OV
DD
OGND
REFOUT REFIN REFP COM REFN
OE
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
MAX1446
ABSOLUTE MAXIMUM RATINGS
V
DD
, OV
DD
to GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
IN+, IN- to GND........................................................-0.3V to V
DD
REFIN, REFOUT, REFP,
REFN, and COM to GND.........................-0.3V to (V
DD
+ 0.3V)
OE,
PD, CLK to GND..................................-0.3V to (V
DD
+ 0.3V)
D9–D0 to GND.........................................-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
32-Pin TQFP (derate 18.7mW/°C above +70°C)......1495.3mW
Operating Temperature Ranges:
MAX1446EHJ+ .................................................-40°C to +85°C
MAX1446GHJ+...............................................-40°C to +105°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3.0V, OV
DD
= 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
≈
10pF at digital outputs, f
CLK
= 62.5MHz
(50% duty cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥+25°C
guaranteed by production test, < +25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT
Input Differential Range
Common-Mode Voltage Range
Input Resistance
Input Capacitance
CONVERSION RATE
Maximum Clock Frequency
Data Latency
DYNAMIC CHARACTERISTICS
f
IN
= 7.492MHz
Signal-to-Noise Ratio
SNR
f
IN
= 19.943MHz
f
IN
= 39.9MHz (Note 1)
Signal-to-Noise + Distortion
(Up to 5th Harmonic)
f
IN
= 7.492MHz
SINAD
f
IN
= 19.943MHz
f
IN
= 39.9MHz (Note 1)
Spurious-Free Dynamic
Range
f
IN
= 7.492MHz
SFDR
f
IN
= 19.943MHz
f
IN
= 39.9MHz (Note 1)
65
63
56.6
56.2
57
56.5
59.5
59.5
59
59.4
59
58.5
74
73
71
dBc
dB
dB
f
CLK
60
5.5
MHz
Cycles
V
DIFF
V
COM
R
IN
C
IN
Switched capacitor load
Differential or single-ended inputs
±1.0
V
DD
/2
±
0.5
33
5
V
V
kΩ
pF
T
A
≥
+25°C
INL
DNL
f
IN
= 7.492MHz, T
A
≥
+25°C
No missing codes, f
IN
= 7.492MHz
-1.6
10
±0.6
±0.4
<
±0.1
0
±1.9
±1.0
±1.9
±2.0
Bits
LSB
LSB
% FS
% FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.0V, OV
DD
= 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
≈
10pF at digital outputs, f
CLK
= 62.5MHz
(50% duty cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥+25°C
guaranteed by production test, < +25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
Third-Harmonic Distortion
Two-Tone Intermodulation
Distortion
Third-Order Intermodulation
Distortion
Total Harmonic Distortion
(First 5 Harmonics)
Small-Signal Bandwidth
Full-Power Bandwidth
Aperture Delay
Aperture Jitter
Overdrive Recovery Time
Differential Gain
Differential Phase
Output Noise
INTERNAL REFERENCE
Reference Output Voltage
Reference Temperature
Coefficient
Load Regulation
REFIN Input Voltage
Positive Reference Output Voltage
Negative Reference Output
Voltage
Common-Mode Level
Differential Reference Output
Voltage Range
REFIN Resistance
Maximum REFP, COM Source
Current
Maximum REFP, COM Sink
Current
REFOUT
TC
REF
2.048
±1%
60
1.25
V
REFIN
V
REFP
V
REFN
V
COM
ΔV
REF
R
REFIN
I
SOURCE
I
SINK
ΔV
REF
= V
REFP
- V
REFN
, T
A
≥
+25°C
0.98
2.048
2.012
0.988
V
DD
/2
1.024
> 50
5
-250
1.07
V
V
V
V
MΩ
mA
µA
V
ppm/°C
mV/mA
IN+ = IN- = COM
FPBW
t
AD
t
AJ
For 1.5
×
full-scale input
SYMBOL
HD3
CONDITIONS
f
IN
= 7.492MHz
f
IN
= 19.943MHz
f
IN
= 39.9MHz (Note 1)
IMD
TT
IM3
f
1
= 19MHz at -6.5dBFS,
f
2
= 21MHz at -6.5dBFS (Note 2)
f
1
= 19MHz at -6.5dBFS
f
2
= 21MHz at -6.5dBFS (Note 2)
f
IN
= 7.492MHz
THD
f
IN
= 19.943MHz
f
IN
= 39.9MHz (Note 1)
Input at -20dBFS, differential inputs
Input at -0.5dBFS, differential inputs
MIN
TYP
-74
-73
-71
-75
-75
-70
-70
-69
500
400
1
2
2
±1
±0.25
0.2
MHz
MHz
ns
psrms
ns
%
°
LSBrms
-64
-63
dBc
dBc
dBc
dBc
MAX
UNITS
MAX1446
BUFFERED EXTERNAL REFERENCE
(V
REFIN
= 2.048V)
_______________________________________________________________________________________
3
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
MAX1446
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.0V, OV
DD
= 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
≈
10pF at digital outputs, f
CLK
= 62.5MHz
(50% duty cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥+25°C
guaranteed by production test, < +25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
Maximum REFN Source Current
Maximum REFN Sink Current
SYMBOL
I
SOURCE
I
SINK
R
REFP
,
R
REFN
C
IN
ΔV
REF
V
COM
V
REFP
V
REFN
ΔV
REF
= V
REFP
- V
REFN
Measured between REFP and COM and
REFN and COM
CONDITIONS
MIN
TYP
250
-5
MAX
UNITS
µA
mA
UNBUFFERED EXTERNAL REFERENCE
(V
REFIN
= AGND, reference voltage applied to REFP, REFN, and COM)
REFP, REFN Input Resistance
REFP, REFN, COM Input
Capacitance
Differential Reference Input
Voltage Range
COM Input Voltage Range
REFP Input Voltage
REFN Input Voltage
DIGITAL OUTPUTS
(CLK, PD,
OE)
CLK
Input High Threshold
V
IH
PD,
OE
CLK
Input Low Threshold
V
IL
PD,
OE
Input Hysteresis
Input Leakage
Input Capacitance
DIGITAL OUTPUTS
(D9–D0)
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
V
OL
V
OH
I
LEAK
C
OUT
I
SINK
= 200µA
I
SOURCE
= 200µA
OE
= OV
DD
OE
= OV
DD
5
OV
DD
-
0.2
±10
0.2
V
V
µA
pF
V
HYST
I
IH
I
IL
C
IN
V
IH
= V
DD
= OV
DD
V
IL
= 0
5
0.1
±5
±5
0.8 x
V
DD
0.8 x
OV
DD
0.2 x
V
DD
0.2 x
OV
DD
V
µA
pF
4
15
1.024
±10%
V
DD
/2
±10%
V
COM
+
ΔV
REF
/2
V
COM
-
ΔV
REF
/2
KΩ
pF
V
V
V
V
V
V
4
_______________________________________________________________________________________
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.0V, OV
DD
= 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
≈
10pF at digital outputs, f
CLK
= 62.5MHz
(50% duty cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥+25°C
guaranteed by production test, < +25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
POWER REQUIREMENTS
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
V
DD
OV
DD
I
VDD
C
L
= 10pF
Operating, f
IN
= 19.943MHz at -0.5dBFS
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, C
L
= 15pF, f
IN
= 19.943MHz at
-0.5dBFS
Shutdown, clock idle, PD =
OE
= OV
DD
Power-Supply Rejection
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
OE
Fall to Output Enable
OE
Rise to Output Disable
Clock Duty Cycle
Wake-Up Time
t
WAKE
t
DO
t
ENABLE
t
DISABLE
Figure 5 (Notes 3, 6)
Figure 5
Figure 5
Figure 6, clock period 16ns (Notes 5, 6)
(Notes 4, 6)
45
366
2
5
10
1.5
55
520
8
ns
ns
ns
%
µs
PSRR
Offset
Gain
2.7
1.7
3.0
3.0
30
4
7
1
±
0.1
±
0.1
20
3.6
3.6
37
15
V
V
mA
µA
mA
µA
mV/V
%/V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1446
Output Supply Current
I
OVDD
Note 1:
SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale
input voltage range.
Note 2:
Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better, if referenced to the two-tone envelope.
Note 3:
Digital outputs settle to V
IH
, V
IL
.
Note 4:
Wake-up time is defined as the time from complete reference power-down until the ADC performs within 0.3 ENOB of the
final performance for f
IN
= 10MHz at -0.5dBFS input amplitude. V
REFIN
= 2.048V, REFP, REFN, and CML decoupled with
2.3µF.
Note 5:
Dynamic characteristics guaranteed at f
IN
= 19.943MHz for the specified duty-cycle range.
Note 6:
Guaranteed by design and engineering characterization.
_______________________________________________________________________________________
5
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