Ordering number : ENA0892B
LC87F5M64A
CMOS IC
FROM 64K byte, RAM 2048 byte on-chip
8-bit 1-chip Microcontroller
Overview
http://onsemi.com
The LC87F5M64A is an 8-bit microcomputer that, integrates on a single chip a number of hardware features such as
64K-byte flash ROM, 2048-byte RAM, On-chip debugging function, a 16-bit timer/counter, four 8-bit timers, a base
timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block
transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports, an 11-channel AD
converter, two 12-bit PWM channels, a system clock frequency divider, and an interrupt feature.
Features
Flash
ROM
•
65536
×
8 bits
•
Capable of on-board-programing
with wide range, 2.7 to 5.5V, of voltage source
•
Block-erasable in 128 byte units
RAM
•
2048
×
9 bits
Package
Form
•
QIP64E (14
×
14) : “Lead-free and halogen-free type”
Package Dimensions
unit : mm (typ)
3159A
17.2
14.0
48
49
33
32
14.0
64
1
0.8
(1.0)
(2.7)
17
16
0.35
0.15
3.0max
0.1
SANYO : QIP64E(14X14)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.02
D1212HK/22912HKIM 20120127-S00009 No. A0892-1/22
17.2
0.8
LC87F5M64A
Minimum
Bus Cycle Time
•
83.3ns (12MHz)
VDD=2.8 to 5.5V
•
125ns (8MHz)
VDD=2.5 to 5.5V
•
500ns (2MHz)
VDD=2.2 to 5.5V
Note: The bus cycle time here refers to the ROM read speed.
Minimum
Instruction Cycle Time (tCYC)
•
250ns (12MHz)
VDD=2.8 to 5.5V
•
375ns (8MHz)
VDD=2.5 to 5.5V
•
1.5μs (2MHz)
VDD=2.2 to 5.5V
Ports
•
Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units
Ports whose I/O direction can be designated in 4-bit units
•
Normal withstand voltage input port
•
Dedicated oscillator ports
•
Reset pins
•
Power pins
46 (P1n, P2n, P3n, P70 to P73, P80 to P86, PCn,
PWM2, PWM3, XT2)
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
6 (VSS1 to 3, VDD1 to 3)
Timers
•
Timer 0: 16-bit timer/counter with a capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
×2
channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
•
Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter
with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler
×
2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8-bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM)
•
Timer 4: 8-bit timer with a 6-bit prescaler
•
Timer 5: 8-bit timer with a 6-bit prescaler
•
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes.
High-speed
Clock Counter
1) Can count clocks with a maximum clock rate of 24MHz (at a main clock of 12MHz)
2) Can generate output real-time.
SIO
•
SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
•
SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
No.A0892-2/22
LC87F5M64A
UART:
2 channels
•
Full duplex
•
7/8/9 bit data bits selectable
•
1 stop bit (2 bit in continuous data transmission)
•
Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
AD
Converter: 8 bits
×
11 channels
PWM:
Multifrequency 12-bit PWM
×
2 channels
Remote
Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an
instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
Watchdog
Timer
•
External RC watchdog timer
•
Interrupt and reset signals selectable
Clock
Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
Interrupts
•
27 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt
requests of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector Address
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/T0L/INT4
INT3/INT5/base timer0/base timer1
T0H/INT6
T1L/T1H/INT7
SIO0/UART1 receive/UART2 receive
SIO1/UART1 transmit/UART2 transmit
ADC/T6/T7
Port 0/T4/T5/PWM2, PWM3
Interrupt Source
•
Priority levels X > H > L
•
Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine
Stack Levels: 1024 levels (the stack is allocated in RAM)
High-speed
Multiplication/Division Instructions
•
16-bits
×
8-bits (5 tCYC execution time)
•
24-bits
×
16-bits (12 tCYC execution time)
•
16-bits
÷
8-bits (8 tCYC execution time)
•
24-bits
÷
16-bits (12 tCYC execution time)
Oscillation
Circuits
•
RC oscillation circuit (internal)
•
CF oscillation circuit
•
Crystal oscillation circuit
•
Multifrequency RC oscillation circuit (internal)
: For system clock
: For system clock, with internal Rf
: For low-speed system clock
: For system clock
No.A0892-3/22
LC87F5M64A
System
Clock Divider Function
•
Can run on low current.
•
The minimum instruction cycle selectable from 250ns, 500ns, 1.0μs, 2.0μs, 4.0μs, 8.0μs, 16.0μs, 32.0μs, and
64.0μs (at a main clock rate of 12MHz).
Standby
Function
•
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt.
•
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
•
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
On-chip
Debugger Function
•
Permits software debugging with the test device installed on the target board.
Development
Tools
•
Evaluation (EVA) chip
•
Emulator
•
On-chip-debugger
Programming
Boards
Package
QIP64E(14
×
14)
Programming boards
W87F50256Q
: LC87EV690
: EVA62S + ECB876600D + SUB875M00 + POD64QFP
ICE-B877300 + SUB875M00 + POD64QFP
: TCB87-TypeB + LC87F5M64A
Flash
ROM Programmer
Maker
Flash Support
Group,
Inc.(Single)
Flash Support
Group, Inc.(Gang)
Model
AF9708/09/09B
(including product of Ando Electric Co.,Ltd)
AF9723(Main body)
(including product of Ando Electric Co.,Ltd)
AF9833(Unit)
(including product of Ando Electric Co.,Ltd)
SKK/SKK Type-B/SKK DBG Type-B
(SANYO FWS)
Support version(Note)
Revision : After Rev.02.73
Device
LC87F6D64A
Revision : After Rev.02.29
LC87F5M64A
Revision : After Rev.01.88
Application Version:
Our company
After 1.04
Chip Data Version:
After2.10
LC87F5M64A
No.A0892-4/22
LC87F5M64A
Pin Assignment
PC5/DBGP0
PC6/DBGP1
PC7/DBGP2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
VDD3
VSS3
PC0
PC1
PC2
PC3
PC4
P30
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN/NKIN
P73/INT3/T0IN
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P10/SO0
P11/SI0/SB0
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
P12/SCK0
2
P13/SO1
3
P14/SI1/SB1
4
P15/SCK1
5
P16/T1PWML
6
P17/T1PWMH/BUZ
7
PWM2
8
PWM3
9 10 11 12 13 14 15 16
VSS2
P00
P01
P02
P03
P04
P05/CKO
VDD2
Top view
32
31
30
29
28
27
26
P32/UTX1
P33/URX1
P34/UTX2
P35/URX2
P36
P37
P27/INT5/T1IN
P26/INT5/T1IN
P25/INT5/T1IN
P24/INT5/T1IN/INT7
P23/INT4/T1IN
P22/INT4/T1IN
P21/INT4/T1IN
P20/INT4/T1IN/INT6
P07/T7O
P06/T6O
P31
25
24
23
22
21
20
19
18
17
LC87F5M64A
QIP64E(14×14) “Lead-free and halogen-free Type”
No.A0892-5/22
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
