Si8450/51/52/55
L
O W
P
O W E R
F
I V E
- C
H A N N E L
D
I G I TA L
I
S O L A T O R
Features
High-speed operation
DC
Up to 2500 V
RMS
isolation
1.6 mA per channel at 1 Mbps
< 6 mA per channel at 100 Mbps
<
Transient Immunity 25 kV/µs
< 1.4 mA per channel at 1 Mbps
Wide temperature range
2.70 V Operation:
<
4 mA per channel at 100 Mbps
High electromagnetic immunity
Applications
Industrial automation systems
Hybrid electric vehicles
Isolated switch mode supplies
Safety Regulatory Approvals
UL 1577 recognized
Up
to 2500 V
RMS
for 1 minute
CSA component notice 5A
approval
IEC
60950-1, 61010-1
(reinforced
insulation)
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS
devices offering substantial data rate, propagation delay, power, size,
reliability, and external BOM advantages when compared to legacy
isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges throughout their
service life. For ease of design, only VDD bypass capacitors are
required.
Data rates up to 150 Mbps are supported, and all devices achieve
worst-case propagation delays of less than 10 ns. All products are
safety certified by UL, CSA, and VDE and support withstand voltages
of up to 2.5 kVrms. These devices are available in a 16-pin narrow-
body SOIC package.
Rev. 1.5 9/13
N
ot
fo R
r N ec
om
ew
m
D e
e s nd
ig e
ns d
ns propagation delay skew
6 ns minimum pulse width
2
60-year life at rated working
No start-up initialization required
voltage
Wide Operating Supply Voltage:
Precise timing (typical)
2.70–5.5 V
<10 ns worst case
Ultra-low-power (typical)
1.5 ns pulse width distortion
5 V Operation:
0.5 ns channel-channel skew
to 150 Mbps
Ordering Information:
See page 29.
–40
to 125 °C at 150 Mbps
narrow body
RoHS-compliant packages
SOIC-16
Isolated ADC, DAC
Motor control
Power inverters
Communications systems
VDE certification conformity
IEC
60747-5-2
(VDE0884 Part 2)
Copyright © 2013 by Silicon Laboratories
Si8450/51/52/55
2
Si8450/51/52/55
Rev. 1.5
N
ot
fo R
r N ec
om
ew
m
D e
e s nd
ig e
ns d
Si8450/51/52/55
T
ABLE
Section
OF
C
ONTENTS
Page
N
ot
fo R
r N ec
om
ew
m
D e
e s nd
ig e
ns d
Rev. 1.5
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1. Enable Pin Causes Outputs to Go Low (Revision A Only) . . . . . . . . . . . . . . . . . . . . 26
3.2. Power Supply Bypass Capacitors (Revision A and Revision B) . . . . . . . . . . . . . . . . 26
3.3. Latch Up Immunity (Revision A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4. Pin Descriptions (Si8450/51/52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5. Pin Descriptions (Si8455) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3
Si8450/51/52/55
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating Temperature*
Supply Voltage
Symbol
T
A
V
DD1
V
DD2
Test Condition
150 Mbps, 15 pF, 5 V
Min
–40
2.70
2.70
Typ
25
—
—
Max
125
5.5
5.5
Unit
°C
V
V
*Note:
The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Absolute Maximum Ratings
1
Parameter
Storage Temperature
2
N
ot
fo R
r N ec
om
ew
m
D e
e s nd
ig e
ns d
Symbol
T
STG
T
A
Min
–65
–40
Typ
—
—
V
DD1
, V
DD2
V
DD1
, V
DD2
V
I
V
O
I
O
–0.5
—
–0.5
—
–0.5
–0.5
—
—
—
—
—
—
—
—
Rev. 1.5
Max
150
125
5.75
6.0
V
DD
+ 0.5
V
DD
+ 0.5
10
260
3600
Unit
°C
°C
V
V
V
V
mA
°C
V
RMS
Ambient Temperature Under Bias
Supply Voltage (Revision A)
3
Supply Voltage (Revision B)
3
Input Voltage
Output Voltage
Output Current Drive Channel
Lead Solder Temperature (10 s)
Maximum Isolation Voltage (1 s)
Notes:
1.
Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2.
VDE certifies storage temperature from –40 to 150 °C.
3.
See "6. Ordering Guide" on page 29 for more information.
4
Si8450/51/52/55
Table 3. Electrical Characteristics
(V
DD1
= 5 V±10%, V
DD2
= 5 V±10%, T
A
= –40 to 125 °C)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Impedance
1
Enable Input High Current
Enable Input Low Current
Si8450Ax, Bx, Si8455Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8451Ax, Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8452Ax, Bx
V
DD1
V
DD2
V
DD1
V
DD2
Symbol
V
IH
V
IL
V
OH
V
OL
I
L
Z
O
I
ENH
I
ENL
Test Condition
Min
2.0
—
Typ
—
—
4.8
0.2
—
85
2.0
2.0
Max
—
0.8
—
0.4
±10
—
—
—
Unit
V
V
V
V
µA
µA
µA
loh = –4 mA
lol = 4 mA
V
DD1
,V
DD2
– 0.4
—
—
—
N
ot
fo R
r N ec
om
ew
m
D e
e s nd
ig e
ns d
V
ENx
= V
IH
V
ENx
= V
IL
—
—
DC Supply Current
(All inputs 0 V or at Supply)
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
—
—
—
—
—
—
—
—
1.6
2.9
7.0
3.1
2.0
3.0
6.0
4.1
2.3
2.7
5.4
4.7
—
—
—
—
—
—
4.3
3.5
4.1
4.0
4.1
4.0
Rev. 1.5
2.4
4.4
10.5
4.7
3.0
4.5
9.0
6.2
3.5
4.1
8.1
7.1
mA
mA
mA
1 Mbps Supply Current
(All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
6.5
5.3
6.2
6.0
6.2
6.0
mA
Si8450Ax, Bx, Si8455Bx
V
DD1
V
DD2
Si8451Ax, Bx
V
DD1
V
DD2
Si8452Ax, Bx
V
DD1
V
DD2
mA
mA
Notes:
1.
The nominal output impedance of an isolator driver channel is approximately 85
,
±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2.
t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3.
See "3. Errata and Design Migration Guidelines" on page 26 for more details.
4.
Start-up time is the time period from the application of power to valid data at the output.
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
