Si824x
C
LASS
D A
UDIO
D
RIVER
Features
0.5 A peak output (Si8241)
4.0 A peak output (Si8244)
WI TH
P
R E C I S I O N
D
E AD
- T
I M E
G
E N E R A T O R
PWM input
High-precision linear programmable
dead-time generator
0.4 ns to 1 µs
High latchup immunity >100 V/ns
Up to 1500 Vrms output-output
isolation, supply voltage of ±750 V
Input to output isolation for low noise
(up to 2500 V)
Up to 8 MHz operation
Wide operating range
–40 to +125 °C
Transient immunity >45 kV/µs
RoHS-compliant
SOIC-16 narrow body
Applications
Class D audio amplifiers
Ordering Information:
See page 25.
Description
The Si824x isolated driver family combines two isolated drivers in a single
package. The Si8241/44 are high-side/low-side drivers specifically targeted at
high-power (>30 W) audio applications. Versions with peak output currents of
0.5 A (Si8241) and 4.0 A (Si8244) are available. All drivers operate with a
maximum supply voltage of 24 V.
Based on Silicon Labs' proprietary isolation technology, the Si824x audio drivers
incorporate input-to-output and output-to-output isolation, which enables level-
translation of signals without additional external circuits as well as use of bipolar
supply voltage up to ±750 V. The Si824x audio drivers feature an integrated dead-
time generator that provides highly precise control for achieving optimal THD.
These products also have overlap protection that safeguards against shoot-
through current damage. The CMOS-based design also provides robust immunity
from latch-up and high-voltage transients. The extremely low propagation delays
enable faster modulation frequencies for an enhanced audio experience. The TTL
level compatible inputs with >400 mV hysteresis are available in PWM input
configuration; other options include UVLO levels of 8 V or 10 V. These products
are available in narrow body SOIC packages.
Pin Assignments
SOIC-16 (Narrow)
PWM
NC
VDDI
GNDI
DISABLE
DT
NC
VDDI
1
2
3
4
5
6
7
8
16
15
14
VDDA
VOA
GNDA
NC
NC
VDDB
VOB
GNDB
Si8241/44
13
12
11
10
9
Functional Block Diagram
PWM
Patents Pending
VDDA
Isolation
DT
VOA
GNDA
VDDI
UVLO
Programmable Dead
Time, Control Gating
VDDB
DISABLE
Isolation
VOB
GNDB
GNDI
Si8241/44
Rev. 1.0 4/14
Copyright © 2014 by Silicon Laboratories
Si824x
Si824x
T
ABLE O F
C
ONTENTS
Section
Page
1. Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1. Typical Performance Characteristics (0.5 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2. Typical Performance Characteristics (4.0 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3. Family Overview and Logic Operation During Startup . . . . . . . . . . . . . . . . . . . . . . . 17
3.4. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.6. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7. Undervoltage Lockout Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8. Programmable Dead Time and Overlap Protection . . . . . . . . . . . . . . . . . . . . . . . . . 22
4. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1. Class D Digital Audio Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.1. Si824x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.2. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 28
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Rev. 1.0
3
Si824x
1. Top-Level Block Diagram
VDDI
PWM
LPWM
ISOLATION
VDDA
VOA
UVLO
GNDA
DT
VDDI
VDDI
UVLO
DT CONTROL
&
OVERLAP
PROTECTION
VDDI
VDDB
ISOLATION
VOB
UVLO
GNDB
DISABLE
LPWM
GNDI
Si8241/44
Figure 1. Si8241/44 Single-Input High-Side/Low-Side Isolated Drivers
4
Rev. 1.0
Si824x
2. Electrical Specifications
Table 1. Electrical Characteristics
1
4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
DC Specifications
Input-Side Power Supply
Voltage
Driver Supply Voltage
Input Supply Quiescent
Current
Output Supply Quiescent
Current
Input Supply Active Current
Output Supply Active Current
Input Pin Leakage Current
Input Pin Leakage Current
Logic High Input Threshold
Logic Low Input Threshold
Input Hysteresis
Logic High Output Voltage
Logic Low Output Voltage
Output Short-Circuit Pulsed
Sink Current
Output Short-Circuit Pulsed
Source Current
Output Sink Resistance
Symbol
Test Conditions
Min
Typ
Max
Units
VDDI
Voltage between VDDA and
VDDA, VDDB GNDA, and VDDB and GNDB
(See “6. Ordering Guide” )
IDDI(Q)
IDDA(Q),
IDDB(Q)
IDDI
IDDO
IPWM
IDISABLE
VIH
VIL
VI
HYST
VOAH,
VOBH
VOAL, VOBL
IOA(SCL),
IOB(SCL)
IOA(SCH),
IOB(SCH)
R
ON(SINK)
IOA, IOB = –1 mA
IOA, IOB = 1 mA
Si8241, Figure 2
Si8244, Figure 2
Si8241, Figure 3
Si8244, Figure 3
Si8241
Si8244
Si8241
Si8244
Si8241/44
Current per channel
PWM freq = 500 kHz
PWM freq = 500 kHz
4.5
—
5.5
V
6.5
—
24
V
—
—
—
—
–10
–10
2.0
—
400
(VDDA
/VDDB)
— 0.04
—
—
—
—
—
—
—
—
—
2
—
2.5
3.6
—
—
—
—
450
—
—
0.5
4.0
0.25
2.0
5.0
1.0
15
2.7
3
3.0
—
—
+10
+10
—
0.8
—
—
0.04
—
—
—
—
—
—
—
—
mA
mA
mA
mA
µA dc
µA dc
V
V
mV
V
V
A
A
A
A
Output Source Resistance
R
ON(SOURCE)
Notes:
1.
VDDA = VDDB = 12 V for 8 V UVLO and 10 V UVLO devices.
2.
The largest RDT resistor that can be used is 220 k.
Rev. 1.0
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
