Smart High-Side Power Switch
BTS5210L
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Data Sheet
1
V1.1, 2007-05-29
Smart High-Side Power Switch
BTS5210L
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control and protection circuit
equivalent to
channel 1
287
Data Sheet
2
V1.1, 2007-05-29
Smart High-Side Power Switch
BTS5210L
Pin Definitions and Functions
Pin
1
2
4
3
5
6,12,
heat
slug
7,9,11
8
10
Symbol Function
GND
Ground
of chip
IN1
Input 1,2
activates channel 1,2 in case of logic
high signal
IN2
ST1
Diagnostic feedback 1 & 2
of channel 1,2
open drain, low on failure
ST2
V
bb
Positive power supply voltage.
Design the
wiring for the simultaneous max. short circuit
currents from channel 1 to 2 and also for low
thermal resistance
NC
Not Connected
OUT2
Output 1,2
protected high-side power output
of channel 1 and 2. Design the wiring for the
OUT1
max. short circuit current
Pin configuration
(top view)
GND
IN1
ST1
IN2
ST2
V
bb
1
•
2
3
4
5
6
V
bb
*
12
11
10
9
8
7
V
bb
NC
OUT1
NC
OUT2
NC
* heat slug
Data Sheet
3
V1.1, 2007-05-29
Smart High-Side Power Switch
BTS5210L
Parameter
Supply voltage (overvoltage protection see page 6)
Supply voltage for full short circuit protection
T
j,start
= -40 ...+150°C
Load current (Short-circuit current, see page 6)
Load dump protection
1
)
V
LoadDump
=
V
A
+
V
s
,
V
A
= 13.5 V
R
I
2
)
= 2
Ω,
t
d
= 400 ms; IN = low or high,
each channel loaded with
R
L
= 13.5
Ω,
Operating temperature range
Storage temperature range
Power dissipation (DC)
4)
T
a
= 25°C:
(all channels active)
T
a
= 85°C:
Maximal switchable inductance, single pulse
V
bb
= 12V,
T
j,start
= 150°C
4)
,
see diagrams on page 10
I
L
= 2.9 A,
E
AS
= 84 mJ, 0
Ω
one channel:
I
L
= 5.7 A,
E
AS
= 168 mJ, 0
Ω
two parallel channels:
Electrostatic discharge capability (ESD)
IN:
(Human Body Model)
ST:
out to all other pins shorted:
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993
R=1.5kΩ; C=100pF
Symbol
Values
43
36
self-limited
60
-40 ...+150
-55 ...+150
3,05
1,59
Unit
V
V
A
V
°C
W
V
bb
V
bb
I
L
V
Load dump3
)
T
j
T
stg
P
tot
Z
L
14
7.6
1.0
4.0
8.0
-10 ... +16
±0.3
±5.0
±5.0
mH
kV
V
ESD
Input voltage (DC)
see internal circuit diagram page 9
Current through input pin (DC)
Pulsed current through input pin
5
)
Current through status pin (DC)
V
IN
I
IN
I
INp
I
ST
V
mA
1
)
2)
3)
4
)
5
)
Supply voltages higher than V
bb(AZ)
require an external current limit for the GND and status pins (a 150Ω
resistor for the GND connection is recommended.
R
I
= internal resistance of the load dump test pulse generator
V
Load dump
is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
2
(one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 14
only for testing
4
V1.1, 2007-05-29
Data Sheet
Smart High-Side Power Switch
BTS5210L
Parameter and Conditions
Thermal resistance
junction - Case
6)
junction – ambient
6)
@ 6 cm
2
cooling area
Symbol
Values
min
typ
max
--
--
--
--
--
--
45
40
5
--
--
--
Unit
each channel:
R
thjC
R
thja
one channel active:
all channels active:
K/W
Electrical Characteristics
Parameter and Conditions,
each of the four channels
at T
j
= -40...+150°C,
V
bb
= 12 V unless otherwise specified
Symbol
Values
min
typ
max
Unit
Load Switching Capabilities and Characteristics
On-state resistance (Vbb to OUT);
IL = 2 A
each channel,
T
j
= 25°C:
R
ON
T
j
= 150°C:
two parallel channels,
T
j
= 25°C:
see diagram, page 11
--
--
--
1.8
3.4
--
110
210
55
2.4
3.9
--
140
280
70
--
mΩ
Nominal load current
one channel active:
I
L(NOM)
two parallel channels active:
A
Device on PCB
6)
,
Ta
=
85°C,
Tj
≤
150°C
Output current
while GND disconnected or pulled up
7
)
;
I
L(GNDhigh)
Vbb = 32 V,
VIN
= 0,
see diagram page 9
Turn-on time
8
)
2
mA
µs
Turn-off time
R
L
= 12
Ω
Slew rate on
8
)
Slew rate off
8
)
IN
IN
to 90%
V
OUT
:
t
on
to 10%
V
OUT
:
t
off
--
--
0.2
0.2
100
100
--
--
250
270
1.0
1.1
10 to 30%
V
OUT
,
R
L
= 12
Ω:
dV/dt
on
70 to 40%
V
OUT
,
R
L
= 12
Ω:
-dV/dt
off
V/µs
V/µs
6
)
7
)
8
)
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
2
(one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 14
not subject to production test, specified by design
See timing diagram on page 12.
5
V1.1, 2007-05-29
Data Sheet