74LVC544ADB: 产品描述Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU; 产品类别逻辑逻辑; 文件大小135KB，共19页; 制造商NXP(恩智浦); 官网地址https://www.nxp.com; 标准

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74LVC544ADB概述

Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU

74LVC544ADB规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	NXP(恩智浦)
包装说明	SSOP, SSOP24,.3
Reach Compliance Code	compliant
其他特性	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型	INDEPENDENT CONTROL
计数方向	BIDIRECTIONAL
系列	LVC/LCX/Z
JESD-30 代码	R-PDSO-G24
JESD-609代码	e4
长度	8.2 mm
逻辑集成电路类型	REGISTERED BUS TRANSCEIVER
最大I（ol）	0.024 A
湿度敏感等级	1
位数	8
功能数量	1
端口数量	2
端子数量	24
最高工作温度	85 °C
最低工作温度	-40 °C
输出特性	3-STATE
输出极性	INVERTED
封装主体材料	PLASTIC/EPOXY
封装代码	SSOP
封装等效代码	SSOP24,.3
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）	260
电源	3.3 V
Prop。Delay @ Nom-Sup	6.5 ns
传播延迟（tpd）	8.5 ns
认证状态	Not Qualified
座面最大高度	2 mm
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	1.2 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式	GULL WING
端子节距	0.65 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	30
翻译	N/A
宽度	5.3 mm
Base Number Matches	1

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74LVC544A

Octal D-type registered transceiver; inverting; 3-state

Rev. 4 — 18 December 2012

Product data sheet

1. General description

The 74LVC544A is an octal registered inverting transceiver containing two sets of D-type

latches for temporary storage of the data flow in either direction. Separate latch enable

inputs (LEAB and LEBA) and output enable inputs (OEAB and OEBA) are provided for

each register to permit independent control of input and output in either direction of the

data flow.

The 74LVC544A contains eight D-type latches, with separate inputs and controls for each

set. For data flow from pins A to B, for example, the A to B enable input (pin EAB) must be

LOW in order to enter data from pins A0 to A7 or take data from pins B0 to B7. With

pin EAB LOW, a LOW signal on the A to B latch enable input (pin LEAB) makes the A to B

latches transparent; a subsequent LOW-to-HIGH transition on pin LEAB puts the A data

into the latches where it is stored and the B outputs no longer change with the A inputs.

With pins EAB and OEAB both LOW, the 3-state B output buffers are active and display

the data present at the outputs of the A latches.

2. Features and benefits



5 V tolerant inputs/outputs for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low-power consumption

Direct interface with TTL levels

8-bit octal transceiver with D-type latch

Back-to-back registers for storage

Separate controls for data flow in each direction

Supports partial power-down applications; inputs/outputs are high-impedance when

= 0 V



Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)



JESD8-C/JESD36 (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-B exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Specified from

40 C

to +85

C

and

40 C

to +125

C

74LVC544ADB相似产品对比

	74LVC544ADB	74LVC544APW	74LVC544AD	74LVC544APW-T	74LVC544ADB-T	74LVC544AD-T
描述	Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU	Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU	Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU	Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU	Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU	Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU
是否Rohs认证	符合	符合	符合	符合	符合	符合
厂商名称	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)
Reach Compliance Code	compliant	unknown	unknown	unknown	unknown	unknown
其他特性	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION	WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
系列	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z
JESD-30 代码	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24
JESD-609代码	e4	e4	e4	e4	e4	e4
长度	8.2 mm	7.8 mm	15.4 mm	7.8 mm	8.2 mm	15.4 mm
逻辑集成电路类型	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER
湿度敏感等级	1	1	1	1	1	1
位数	8	8	8	8	8	8
功能数量	1	1	1	1	1	1
端口数量	2	2	2	2	2	2
端子数量	24	24	24	24	24	24
最高工作温度	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
输出极性	INVERTED	INVERTED	INVERTED	INVERTED	INVERTED	INVERTED
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	SSOP	TSSOP	SOP	TSSOP	SSOP	SOP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE
峰值回流温度（摄氏度）	260	260	260	260	260	260
传播延迟（tpd）	8.5 ns	8.5 ns	8.5 ns	8.5 ns	8.5 ns	8.5 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	2 mm	1.1 mm	2.65 mm	1.1 mm	2 mm	2.65 mm
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.65 mm	0.65 mm	1.27 mm	0.65 mm	0.65 mm	1.27 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	30	30	30	30	30	30
宽度	5.3 mm	4.4 mm	7.5 mm	4.4 mm	5.3 mm	7.5 mm
Base Number Matches	1	1	1	1	1	1

74LVC544ADB

74LVC544ADB在线购买

74LVC544ADB概述

74LVC544ADB规格参数

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74LVC544ADB相似产品对比

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