STK850
N-channel 30V - 0.0024Ω - 30A - PolarPAK
®
STripFET™ Power MOSFET
Features
Type
STK850
■
■
■
■
■
■
V
DSS
30V
R
DS(on)
<0.0029Ω
R
DS(on)
*Q
g
71nC*mΩ
P
TOT
5.2W
Ultra low top and bottom junction to case
thermal resistance
Very low capacitances
100% Rg tested
Fully encapsulated die
100% Matte tin finish (in compliance with the
2002/95/EC european directive)
PolarPAK
®
is a trademark of VISHAY
PolarPAK
®
Application
■
Switching applications
Description
bs
O
This Power MOSFET is the latest development of
STMicroelectronics unique “single feature size”
strip-based process. The resulting transistor
shows extremely high packing density for low on-
resistance, moreover the double sides cooling
package with ultra low junction to case thermal
resistance allows to handle higher levels of
current.
et
l
o
ro
P
e
uc
d
s)
t(
O
-
Figure 1.
so
b
te
le
ro
P
uc
d
s)
t(
Internal schematic diagram
Bottom View
Top View
Table 1.
Device summary
Order code
STK850
Marking
K850
Package
PolarPAK
®
Packaging
Tape & reel
October 2007
Rev 9
1/16
www.st.com
16
Contents
STK850
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................. 6
3
4
5
Test circuits
.............................................. 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
bs
O
et
l
o
ro
P
e
uc
d
s)
t(
O
-
so
b
te
le
ro
P
uc
d
s)
t(
2/16
STK850
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
V
DS
V
GS (1)
V
GS(2)
I
D (4)
I
D
I
DM (3)
P
TOT (4)
Absolute maximum ratings
Parameter
Drain-source voltage (V
GS
= 0)
Gate-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25°C
Drain current (continuous) at T
C
= 100°C
Drain current (pulsed)
Total dissipation at T
C
= 25°C
Derating factor
Value
30
± 16
± 18
30
18.75
Unit
V
V
V
E
AS (5)
T
J
T
stg
Single pulse avalanche energy
Operating junction temperature
Storage temperature
1. Continuous mode
2. Guaranteed for test time < 15ms
3. Pulse width limited by package
4. When mounted on FR-4 board of 1inch
2
, 2 oz. Cu. and
≤
10sec
5. Starting T
J
= 25°C, I
D
= 15A, V
DD
= 25V
Table 3.
bs
O
et
l
o
3.
Symbol
Rthj-amb
(1)
Thermal resistance junction-amb
Rthj-c
(2)
Rthj-c
(3)
Thermal resistance junction-case (top drain)
Thermal resistance junction-case (source)
ro
P
e
Thermal data
Parameter
Typ.
20
0.8
2.2
Max.
24
1
2.7
Unit
°C/W
°C/W
°C/W
uc
d
)-
(s
t
b
O
so
te
le
r
P
0.0416
1.4
d
o
5.2
120
uc
s)
t(
A
A
A
W
W/°C
J
°C
-55 to 150
1. When mounted on FR-4 board of 1inch
2
, 2 oz. Cu. and
≤
10sec
2.
Steady State
Measured at Source pin when the device is mounted on FR-4 board in steady state
3/16
Electrical characteristics
STK850
2
Electrical characteristics
(T
CASE
=25°C unless otherwise specified)
Table 4.
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
On/off
Parameter
Drain-source breakdown
voltage
Zero gate voltage drain
current (V
GS
= 0)
Gate body leakage current
(V
DS
= 0)
Gate threshold voltage
Static drain-source on
resistance
Test conditions
I
D
= 250µA, V
GS
= 0
V
DS
= Max rating,
V
DS
= Max rating,Tc=125°C
V
GS
= ±16V
V
DS
= V
GS
, I
D
= 250µA
V
GS
= 10V, I
D
= 15A
V
GS
= 4.5V, I
D
= 15A
Min.
30
1
10
Typ.
Max.
Unit
V
µA
µA
Table 5.
Symbol
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
Dynamic
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
bs
O
et
l
o
Q
gs1
ro
P
e
R
G
Total gate charge
Gate-source charge
Gate-drain charge
uc
d
s)
t(
O
-
so
b
te
le
ro
P
Min.
1
0.0024 0.0029
0.0029 0.0035
uc
d
Typ.
3150
940
90
24.5
8
8.2
0.6
7.2
±
100
s)
t(
2.5
nA
V
Ω
Ω
Test conditions
Max.
Unit
pF
pF
pF
V
DS
=25V, f=1 MHz, V
GS
=0
V
DD
=15V, I
D
= 30A
V
GS
=4.5V
(see Figure 16)
V
DD
=15V, I
D
= 12A
V
GS
=4.5V
(see Figure 21)
f=1 MHz Gate DC Bias = 0
Test signal level = 20mV
open drain
32.5
nC
nC
nC
nC
nC
Q
gs2
Pre V
th
gate-to-source
charge
Post V
th
gate-to-source
charge
Gate input resistance
1.1
Ω
4/16
STK850
Electrical characteristics
Table 6.
Symbol
t
d(on)
t
r
t
d(off)
t
f
Switching times
Parameter
Turn-on delay time
Rise time
Test conditions
V
DD
= 15V, I
D
= 15A,
R
G
=4.7Ω, V
GS
=4.5V
(see Figure 15)
V
DD
=15V, I
D
= 15A,
R
G
=4.7Ω, V
GS
=4.5V
(see Figure 15)
Min.
Typ.
20
57
Max.
Unit
ns
ns
Turn-off delay time
Fall time
31
13
ns
ns
Table 7.
Symbol
I
SD
I
SDM
(1)
Source drain diode
Parameter
Source-drain current
Source-drain current
(pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 15A, V
GS
=0
Test conditions
Min.
V
SD (2)
t
rr
Q
rr
I
RRM
I
SD
= 30A, di/dt = 100A/µs,
V
DD
=20V, T
J
=150°C
(see Figure 20)
1. Pulse width limited by package
2. Pulsed: pulse duration = 300µs, duty cycle 1.5%
bs
O
et
l
o
ro
P
e
uc
d
s)
t(
O
-
so
b
te
le
ro
P
uc
d
39
39.8
2
Typ.
Max.
30
120
1.2
s)
t(
Unit
A
A
V
ns
nC
A
5/16