IR3504
DATA SHEET
XPHASE3
TM
AMD SVID CONTROL IC
DESCRIPTION
The IR3504 Control IC combined with an
xPHASE3
Phase IC provides a full featured and flexible way to
implement a complete AMD SVID power solution. It provides outputs for both the VDD core and VDDNB
auxiliary planes required by the CPU. The IR3504 provides overall system control and interfaces with any
TM
number of Phase ICs each driving and monitoring a single phase. The
xPHASE3
architecture results in a
power supply that is smaller, less expensive, and easier to design while providing higher efficiency than
conventional approaches.
TM
FEATURES
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2 converter outputs for the AMD processor VDD core and VDDNB auxiliary planes
AMD Serial VID interface independently programs both output voltages and operation
Both Converter Outputs boot to 2-bit “Boot” VID codes which are read and stored from the SVC & SVD
parallel inputs upon the assertion of the Enable input
PWROK input signal activates SVID after successful boot start-up
Both Converter Outputs can be independently turned on and off through SVID commands
Deassertion of PWROK prior to Enable causes the converter output to transition to the stored Pre-
PWROK VID codes
Connecting the PWROK input to VCCL disables SVID and implements VFIX mode with both output
voltages programmed via SVC & SVD parallel inputs per the 2 bit VFIX VID codes
PG monitors output voltage, PG will deassert if either ouput voltage out of spec
0.5% overall system set point accuracy
Programmable Dynamic VID Slew Rates
Programmable VID Offset (VDD output only)
Programmable output impedance (VDD output only)
High speed error amplifiers with wide bandwidth of 20MHz and fast slew rate of 10V/us
Remote sense amplifiers provide differential sensing and require less than 50uA bias current
Programmable per phase switching frequency of 250kHz to 1.5MHz
Daisy-chain digital phase timing provides accurate phase interleaving without external components
Hiccup over current protection with delay during normal operation
Central over voltage detection and communication to phase ICs through IIN (ISHARE) pin
OVP disabled during dynamic VID down to prevent false triggering
Detection and protection of open remote sense lines
Gate Drive and IC bias linear regulator control with programmable output voltage and UVLO
Simplified Power Good (PG) Output provides indication of proper operation and avoids false triggering
Small thermally enhanced 32L MLPQ (5mm x 5mm) package
Over voltage signal to system with over voltage detection during powerup and normal operation
ORDERING INFORMATION
Device
IR3504MTRPBF
* IR3504MPBF
* Samples only
Package
32 Lead MLPQ (5 x 5 mm body)
32 Lead MLPQ (5 x 5 mm body)
Order Quantity
3000 per reel
100 piece strips
Page 1
July 28, 2009
IR3504
APPLICATION CIRCUIT
12V
Q1
RVCCLFB1
RVCCLDRV
PHSIN
RVCCLFB2
CVCCL
12V
VCCL
To Converters
To Phase IC
VCCL & GATE
DRIVE BIAS
Power Good
31
30
29
28
27
32
26
25
SVC
SVD
PWROK
ENABLE
CSS/DEL2
CVDAC2
1
2
3
4
5
RVDAC2
6
7
8
SVD
PWROK
ENABLE
IIN2
SS/DEL2
VDAC2
OCSET2
VOSNS2+
VOSNS1+
VONSN1-
VOSNS2-
EAOUT2
VOUT2
FB2
LGND
ROSC
24
23
22
21
20
RVDAC1
19
18
17
CDRP1
RDRP1
ROCSET1
CSS/DEL1
CVDAC1
ROSC
Phase Clock Input to
Last Phase IC of VDD
PHSOUT
2 wire
Digital
CLKOUT
Daisy Chain
Bus to VDD
& VDDNB
Phase ICs
PG
VCCLDRV
VCCLFB
VCCL
PHSIN
SVC
PHSOUT
CLKOUT
VDRP1
IIN1
SS/DEL1
VDAC1
OCSET1
EAOUT1
IR3504
CONTROL
IC
ISHARE1
VDAC1
EAOUT1
ROCSET2
3 Wire Analog
Control Bus
to VDD Phase
ICs
VOUT1
15
10
11
12
13
14
16
9
FB1
RCP2
CCP21
RFB22
RFB21
CFB2
CFB1
RFB12
RCP1
CCP11
RTHERMISTOR1
CCP22
RFB11
CCP12
Load Line NTC
Thermistor;
Locate close to
VDD Power Stage
VDD SENSE +
VDD SENSE -
EAOUT2
VDAC2
ISHARE2
RFB13
To VDD
Remote
Sense
3 Wire Analog
Control Bus to
VDDNB Phase
ICs
To VDDNB
Remote
Sense
VDDNB SENSE -
VDDNB SENSE +
Figure 1 – IR3504 Application Circuit
PIN DESCRIPTION
PIN#
1
PIN SYMBOL
SVD
PIN DESCRIPTION
SVD (Serial VID Data) is a bidirectional signal that is an input and open drain output
for both master (AMD processor) and slave (IR3504), requires an external bias
voltage and should not be floated
System wide Power Good signal and input to the IR3504. When asserted, the
IR3504 output voltage is programmed through the SVID interface protocol.
Connecting this pin to VCCL enables VFIX mode.
Enable input. A logic low applied to this pin puts the IC into fault mode. A logic high
on the pin enables the converter and causes the SVC and SVD input states to be
decoded and stored, determining the 2-bit Boot VID. Do not float this pin as the logic
state will be undefined.
Output 2 average current input from the output 2 phase IC(s). This pin is also used
to communicate over voltage condition to the output 2 phase ICs.
Programs output 2 startup and over current protection delay timing. Connect an
external capacitor to LGND to program.
Output 2 reference voltage programmed by the SVID inputs and error amplifier non-
inverting input. Connect an external RC network to LGND to program dynamic VID
slew rate and provide compensation for the internal buffer amplifier.
Programs the output 2 constant converter output current limit and hiccup over-
current threshold through an external resistor tied to VDAC2 and an internal current
source from this pin. Over-current protection can be disabled by connecting a
resistor from this pin to VDAC2 to program the threshold higher than the possible
signal into the IIN2 pin from the phase ICs but no greater than 5V (do not float this
pin as improper operation will occur).
2
PWROK
3
ENABLE
4
5
6
IIN2
SS/DEL2
VDAC2
7
OCSET2
Page 2
July 28, 2009
IR3504
PIN#
8
9
10
11
12
13
14
15
16
PIN SYMBOL
EAOUT2
FB2
VOUT2
VOSEN2+
VOSEN2-
VOSEN1-
VOSEN1+
VOUT1
FB1
PIN DESCRIPTION
Output of the output 2 error amplifier.
Inverting input to the Output 2 error amplifier.
Output 2 remote sense amplifier output.
Output 2 remote sense amplifier input. Connect to output at the load.
Output 2 remote sense amplifier input. Connect to ground at the load.
Output 1 remote sense amplifier input. Connect to ground at the load.
Output 1 remote sense amplifier input. Connect to output at the load.
Output 1 remote sense amplifier output.
Inverting input to the output 1 error amplifier. Converter output voltage can be
increased from the VDAC1 voltage with an external resistor connected between
VOUT1 and this pin (there is an internal current sink at this pin).
Output of the output 1 error amplifier.
Programs the output 1 constant converter output current limit and hiccup over-
current threshold through an external resistor tied to VDAC1 and an internal current
source from this pin. Over-current protection can be disabled by connecting a
resistor from this pin to VDAC1 to program the threshold higher than the possible
signal into the IIN1 pin from the phase ICs but no greater than 5V (do not float this
pin as improper operation will occur).
Output 1 reference voltage programmed by the SVID inputs and error amplifier non-
inverting input. Connect an external RC network to LGND to program dynamic VID
slew rate and provide compensation for the internal buffer amplifier.
Programs output 1 startup and over current protection delay timing. Connect an
external capacitor to LGND to program.
Output 1 average current input from the output 1 phase IC(s). This pin is also used
to communicate over voltage condition to phase ICs.
Output 1 Buffered IIN1 signal. Connect an external RC network to FB1 to program
converter output impedance.
Connect a resistor to LGND to program oscillator frequency and OCSET1, OCSET2,
FB1, FB2, VDAC1, and VDAC2 bias currents. Oscillator frequency equals switching
frequency per phase. The pin voltage is 0.6V during normal operation and higher
than 1.6V if over-voltage condition is detected.
Local Ground for internal circuitry and IC substrate connection.
Clock output at switching frequency multiplied by phase number. Connect to CLKIN
pins of phase ICs.
Phase clock output at switching frequency per phase. Connect to PHSIN pin of the
first phase IC.
Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC.
Output of the voltage regulator, and power input for clock oscillator circuitry. Connect
a decoupling capacitor to LGND.
Non-inverting input of the voltage regulator error amplifier. Output voltage of the
regulator is programmed by the resistor divider connected to VCCL.
Output of the VCCL regulator error amplifier to control external transistor. The pin
senses 12V power supply through a resistor.
Power good signal implemented with an open collector output that drives low during
startup and under any external fault condition. Also, if any of the voltage planes fall
out of spec, it will drive low. Connect external pull-up. (Output voltage out of spec is
defined as 350mV to 240mV below VDAC voltages)
SVC (Serial VID Clock) is an open drain output of the processor and input to
IR3504, requires an external bias voltage and should not be floated
17
18
EAOUT1
OCSET1
19
VDAC1
20
21
22
23
SS/DEL1
IIN1
VDRP1
ROSC/OVP
24
25
26
27
28
29
30
31
LGND
CLKOUT
PHSOUT
PHSIN
VCCL
VCCLFB
VCCLDRV
PG
32
SVC
Page 3
July 28, 2009
IR3504
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur.
All voltages are absolute voltages referenced to the LGND pin.
Operating Junction Temperature……………..0 to 150 C
o
o
Storage Temperature Range………………….-65 C to 150 C
ESD Rating………………………………………HBM Class 1C JEDEC Standard
MSL Rating………………………………………2
o
Reflow Temperature…………………………….260 C
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN NAME
SVD
PWROK
ENABLE
IIN2
SS/DEL2
VDAC2
OCSET2
EAOUT2
FB2
VOUT2
VOSEN2+
VOSEN2-
VOSEN1-
VOSEN1+
VOUT1
FB1
EAOUT1
OCSET1
VDAC1
IIN1
SS/DEL1
VDRP1
ROSC/OVP
LGND
CLKOUT
PHSOUT
PHSIN
VCCL
VCCLFB
VCCLDRV
PG
SVC
V
MAX
8V
8V
3.5V
8V
8V
3.5V
8V
8V
8V
8V
8V
1.0V
1.0V
8V
8V
8V
8V
8V
3.5V
8V
8V
8V
8V
n/a
8V
8V
8V
8V
3.5V
10V
VCCL + 0.3V
8V
V
MIN
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
n/a
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
I
SOURCE
1mA
1mA
1mA
5mA
1mA
1mA
1mA
25mA
1mA
5mA
5mA
5mA
5mA
5mA
5mA
1mA
25mA
1mA
1mA
5mA
1mA
35mA
1mA
20mA
100mA
10mA
1mA
1mA
1mA
1mA
1mA
1mA
I
SINK
10mA
1mA
1mA
1mA
1mA
1mA
1mA
10mA
1mA
25mA
1mA
1mA
1mA
1mA
25mA
1mA
10mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
100mA
10mA
1mA
20mA
1mA
50mA
20mA
1mA
o
Page 4
July 28, 2009
IR3504
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
4.75V
≤
VCCL
≤
7.5V, -0.3V
≤
VOSEN-x
≤
0.3V, 0 C
≤
T
J
≤
100 C, 7.75 k
o
o
≤
R
OSC
≤
50 k , C
SS/DELx
= 0.1uF
ELECTRICAL CHARACTERISTICS
The electrical characteristics involve the spread of values guaranteed within the recommended operating
conditions (unless otherwise specified). Typical values represent the median values, which are related to 25°C.
PARAMETER
SVID Interface
SVC & SVD Input Thresholds
TEST CONDITION
Threshold Increasing (Note 1)
Threshold Decreasing (Note 1)
Threshold Hysteresis (Note 1)
0V
≤
V(x)
≤
3.5V, SVD not asserted
I(SVD)= 3mA
0.7 x VDDIO to 0.3VDDIO, 1.425V
≤
VDDIO
≤
1.9V, 10 pF
≤
Cb
≤
400 pF,
Cb=capacitance of one bus line (Note 1)
Note 1
MIN
0.850
550
195
-5
20+ 0.1
xCb(pF)
97
TYP
0.950
650
300
0
20
MAX
1.05
750
405
5
300
250
UNIT
V
mV
mV
uA
mV
ns
Bias Current
SVD Low Voltage
SVD Output Fall Time
Pulse width of spikes suppressed
by the input filter
260
410
ns
Oscillator
PHSOUT Frequency
ROSC Voltage
CLKOUT High Voltage
CLKOUT Low Voltage
PHSOUT High Voltage
PHSOUT Low Voltage
PHSIN Threshold Voltage
-10%
0.57
I(CLKOUT)= -10 mA, measure V(VCCL) –
V(CLKOUT).
I(CLKOUT)= 10 mA
I(PHSOUT)= -1 mA, measure V(VCCL) –
V(PHSOUT)
I(PHSOUT)= 1 mA
Compare to V(VCCL)
V(VDRP1) – V(IIN1), 0.5V
≤
V(IIN)
≤
3.3V
0.5V
≤
V(IIN1)
≤
3.3V
0.5V
≤
V(IIN1)
≤
3.3V
Note 1
Note 1
See
Figure 2
0.600
+10%
0.630
1
1
1
1
70
8
30
0.6
kHz
V
V
V
V
V
%
mV
mA
mA
MHz
V/µs
µA
MHz
mV
mA
mA
V/us
uA
uA
V
mV
V
ms
ms
30
-8
2
0.2
50
0
0.4
8
4.7
0
6.4
0
1
12
4
30
30
VDRP1 Buffer Amplifier
Input Offset Voltage
Source Current
Sink Current
Unity Gain Bandwidth
Slew Rate
IIN Bias Current
Unity Gain Bandwidth
Input Offset Voltage
Source Current
Sink Current
Slew Rate
VOSEN+ Bias Current
VOSEN- Bias Current
VOSEN+ Input Voltage Range
Low Voltage
High Voltage
Soft Start and Delay
Start Delay
Start-up Time
-1
Note 1
0.5V≤ V(VOSENx+) - V(VOSENx-)
≤
1.6V,
Note 2
0.5V≤ V(VOSENx+) - V(VOSENx-)
≤
1.6V
0.5V≤ V(VOSENx+) - V(VOSENx-)
≤
1.6V
0.5V≤ V(VOSENx+) - V(VOSENx-)
≤
1.6V
0.5 V < V(VOSENx+) < 1.6V
-0.3V
≤
VOSENx-
≤
0.3V, All VID Codes
V(VCCL)=7V
V(VCCL) =7V
V(VCCL) – V(VOUTx)
Measure Enable to EAOUTx activation
Measure Enable activation to PG
3.0
-3
0.5
2
2
1
9.0
3
1.7
16
8
50
55
5.5
250
1
3.5
13
Remote Sense Differential Amplifiers
0.5
1
3
2.9
8
Page 5
July 28, 2009
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