IRLHS6342PbF
HEXFET
®
Power MOSFET
V
DS
V
GS
R
DS(on) max
(@V
GS
= 4.5V)
30
±12
15.5
11
12
V
V
mΩ
nC
A
D 1
TOP VIEW
6 D
D
D
D
D
Q
g (typical)
I
D
(@T
C (Bottom)
= 25°C)
D 2
S
D
5 D
G
i
G 3
4 S
D
S
S
2mm x 2mm PQFN
Applications
•
Charge and discharge switch for battery application
•
System/Load Switch
Features and Benefits
Features
Low R
DSon
(≤ 15.5mΩ)
Low Thermal Resistance to PCB (≤ 13°C/W)
Low Profile (≤ 0.9 mm)
Compatible with Existing Surface Mount Techniques
RoHS Compliant Containing no Lead, no Bromide and no Halogen
MSL1, Industrial Qualification
Resulting Benefits
Lower Conduction Losses
Enable better thermal dissipation
Increased Power Density
Easier Manufacturing
Environmentally Friendlier
Increased Reliability
results in
Orderable part number
IRLHS6342TRPbF
IRLHS6342TR2PbF
Package Type
PQFN 2mm x 2mm
PQFN 2mm x 2mm
Standard Pack
Form
Quantity
Tape and Reel
Tape and Reel
4000
400
Note
EOL notice # 259
Absolute Maximum Ratings
Parameter
V
DS
V
GS
I
D
@ T
A
= 25°C
I
D
@ T
A
= 70°C
I
D
@ T
C(Bottom)
= 25°C
I
D
@ T
C(Bottom)
= 70°C
I
D
@ T
C(Bottom)
= 25°C
I
DM
P
D
@T
A
= 25°C
P
D
@T
A
= 70°C
T
J
T
STG
Drain-to-Source Voltage
Gate-to-Source Voltage
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V (Wirebond Limited)
Pulsed Drain Current
Power Dissipation
g
Power Dissipation
g
Max.
30
±12
8.7
6.9
19
Units
V
c
hi
15
hi
12
i
76
2.1
1.3
A
W
W/°C
°C
Linear Derating Factor
Operating Junction and
g
0.02
-55 to + 150
Storage Temperature Range
Notes
through
are on page 2
1
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2013 International Rectifier
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December 17, 2013
IRLHS6342PbF
Static @ T
J
= 25°C (unless otherwise specified)
Parameter
BV
DSS
ΔΒV
DSS
/ΔT
J
R
DS(on)
V
GS(th)
ΔV
GS(th)
I
DSS
I
GSS
gfs
Q
g
Q
gs
Q
gd
R
G
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Parameter
Single Pulse Avalanche Energy
Avalanche Current
Min.
30
–––
–––
–––
0.5
–––
–––
–––
–––
–––
39
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
22
12.0
15.0
–––
-4.2
–––
–––
–––
–––
–––
11
0.5
4.6
2.1
4.9
13
19
13
1019
97
70
Max. Units
–––
–––
15.5
19.5
1.1
–––
1.0
150
100
-100
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
–––
Ω
ns
V
Conditions
V
GS
= 0V, I
D
= 250μA
mV/°C Reference to 25°C, I
D
= 1mA
V
GS
= 4.5V, I
D
= 8.5A
mΩ
V
GS
= 2.5V, I
D
= 8.5A
V
V
DS
= V
GS
, I
D
= 10μA
mV/°C
e
e
μA
nA
S
nC
V
DS
= 24V, V
GS
= 0V
V
DS
= 24V, V
GS
= 0V, T
J
= 125°C
V
GS
= 12V
V
GS
= -12V
V
DS
= 10V, I
D
= 8.5A
V
DS
= 15V
V
GS
= 4.5V
I
D
= 8.5A (See Fig. 6 & 17)
V
DD
= 15V, V
GS
= 4.5V
I
D
= 8.5A
R
G
=1.8Ω
See Fig.18
V
GS
= 0V
V
DS
= 25V
ƒ = 1.0MHz
Max.
14
8.5
Units
mJ
A
pF
Avalanche Characteristics
E
AS
I
AR
d
Min.
–––
–––
–––
–––
Diode Characteristics
Parameter
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Typ.
–––
–––
–––
11
Max. Units
12
Conditions
MOSFET symbol
D
i
A
V
ns
Ã
76
1.2
17
showing the
integral reverse
G
S
–––
13
20
nC
Time is dominated by parasitic Inductance
p-n junction diode.
T
J
= 25°C, I
S
= 8.5A, V
GS
= 0V
T
J
= 25°C, I
F
= 8.5A, V
DD
= 15V
di/dt = 300 A/μs
e
eÃ
Thermal Resistance
R
θJC
(Bottom)
R
θJC
(Top)
R
θJA
R
θJA
Junction-to-Case
Junction-to-Case
Junction-to-Ambient
Junction-to-Ambient (<10s)
g
g
Parameter
f
f
Typ.
–––
–––
–––
–––
Max.
13
90
60
42
Units
°C/W
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Starting T
J
= 25°C, L = 0.39mH, R
G
= 50Ω, I
AS
= 8.5A.
Pulse width
≤
400μs; duty cycle
≤
2%.
R
θ
is measured at
T
J
of approximately 90°C.
When mounted on 1 inch square 2 oz copper pad on 1.5x1.5 in. board of FR-4 material.
Calculated continuous current based on maximum allowable junction temperature.
Package is limited to 12A by die-source to lead-frame bonding technology
2
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December 17, 2013
IRLHS6342PbF
100
TOP
VGS
10V
4.5V
3.0V
2.5V
2.0V
1.8V
1.5V
1.4V
100
TOP
VGS
10V
4.5V
3.0V
2.5V
2.0V
1.8V
1.5V
1.4V
ID, Drain-to-Source Current (A)
10
BOTTOM
ID, Drain-to-Source Current (A)
BOTTOM
10
1
1.4V
1.4V
≤
60μs PULSE WIDTH
Tj = 25°C
0.1
0.1
1
10
100
V DS, Drain-to-Source Voltage (V)
≤
60μs PULSE WIDTH
Tj = 150°C
1
0.1
1
10
100
V DS, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
Fig 2.
Typical Output Characteristics
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
ID = 8.5A
VGS = 4.5V
ID, Drain-to-Source Current (A)
TJ = 150°C
10
TJ = 25°C
VDS = 15V
≤
60μs PULSE WIDTH
1.0
1.0
1.5
2.0
2.5
3.0
3.5
-60 -40 -20 0
20 40 60 80 100 120 140 160
VGS, Gate-to-Source Voltage (V)
T J , Junction Temperature (°C)
Fig 3.
Typical Transfer Characteristics
10000
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
C oss = C ds + C gd
Fig 4.
Normalized On-Resistance vs. Temperature
14.0
ID= 8.5A
VGS, Gate-to-Source Voltage (V)
12.0
10.0
8.0
6.0
4.0
2.0
0.0
C, Capacitance (pF)
1000
Ciss
VDS= 24V
VDS= 15V
VDS= 6.0V
100
Coss
Crss
10
1
10
VDS, Drain-to-Source Voltage (V)
100
0
5
10
15
20
25
30
QG, Total Gate Charge (nC)
Fig 5.
Typical Capacitance vs.Drain-to-Source Voltage
3
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2013 International Rectifier
Fig 6.
Typical Gate Charge vs.Gate-to-Source Voltage
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December 17, 2013
IRLHS6342PbF
100
1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ISD, Reverse Drain Current (A)
ID, Drain-to-Source Current (A)
T J = 150°C
10
T J = 25°C
100
100μsec
10
Limited by
Wire Bond
1
Tc = 25°C
Tj = 150°C
Single Pulse
0.1
0
1
1msec
10msec
DC
VGS = 0V
1.0
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
VSD, Source-to-Drain Voltage (V)
10
100
VDS, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode Forward Voltage
20
Limited By Package
VGS(th) , Gate threshold Voltage (V)
Fig 8.
Maximum Safe Operating Area
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
ID = 10μA
ID = 25μA
18
16
ID, Drain Current (A)
14
12
10
8
6
4
2
0
25
50
75
100
125
150
T C , Case Temperature (°C)
ID = 250μA
ID = 1.0mA
ID = 1.0A
-75 -50 -25
0
25
50
75 100 125 150
T J , Temperature ( °C )
Fig 9.
Maximum Drain Current vs.
Case (Bottom) Temperature
100
Thermal Response ( Z thJC ) °C/W
Fig 10.
Threshold Voltage vs. Temperature
10
D = 0.50
0.20
0.10
0.05
0.02
0.01
1
0.1
SINGLE PULSE
( THERMAL RESPONSE )
0.01
1E-006
1E-005
0.0001
0.001
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case (Bottom)
4
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December 17, 2013
IRLHS6342PbF
RDS(on) , Drain-to -Source On Resistance (m
Ω)
RDS(on), Drain-to -Source On Resistance ( mΩ)
30
ID = 8.5A
25
30
28
26
24
22
20
18
16
14
12
10
5
15
25
35
45
55
65
75
ID, Drain Current (A)
Vgs = 4.5V
Vgs = 2.5V
20
T J = 125°C
15
10
T J = 25°C
5
0
2
4
6
8
10
12
14
Fig 12.
On-Resistance vs. Gate Voltage
60
EAS , Single Pulse Avalanche Energy (mJ)
VGS, Gate -to -Source Voltage (V)
Fig 13.
Typical On-Resistance vs. Drain Current
600
50
40
30
20
10
0
25
50
75
Single Pulse Power (W)
ID
TOP
1.9A
3.4A
BOTTOM 8.5A
500
400
300
200
100
0
1E-5
100
125
150
1E-4
1E-3
1E-2
1E-1
1E+0
Starting T J , Junction Temperature (°C)
Time (sec)
Fig 14.
Maximum Avalanche Energy vs. Drain Current
Fig 15.
Typical Power vs. Time
Driver Gate Drive
D.U.T
+
P.W.
Period
D=
P.W.
Period
V
GS
=10V
-
+
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
*
D.U.T. I
SD
Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V
DS
Waveform
Diode Recovery
dv/dt
-
-
+
R
G
•
dv/dt controlled by R
G
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor "D"
•
D.U.T. - Device Under Test
V
DD
V
DD
+
-
Re-Applied
Voltage
Inductor Curent
Body Diode
Forward Drop
Ripple
≤
5%
I
SD
*
V
GS
= 5V for Logic Level Devices
Fig 16.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
5
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December 17, 2013
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