74LVQ245
LOW VOLTAGE CMOS OCTAL BUS
TRANSCEIVER WITH (3-STATE)
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DESCRIPTION
The 74LVQ245 is a low voltage CMOS OCTAL
BUS TRANSCEIVER (3-STATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for low power
and low noise 3.3V applications.
Figure 1: Pin Connection And IEC Logic Symbols
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Pr
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SOP
TSSOP
HIGH SPEED:
t
PD
= 5.7 ns (TYP.) at V
CC
= 3.3 V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 5
µA
(MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.5V (TYP.) at V
CC
= 3.3V
75Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 245
IMPROVED LATCH-UP IMMUNITY
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ245MTR
74LVQ245TTR
This IC is intended for two-way asynchronous
communication between data buses and the
direction of data transmission is determined by
DIR input. The enable input G can be used to
disable the device so that the buses are effectively
isolated.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
All floating bus terminals during High Impedance
State must be held HIGH or LOW.
July 2004
Rev. 5
1/12
74LVQ245
Figure 2: Input Equivalent Circuit
Table 2: Pin Description
PIN N°
1
2, 3, 4, 5, 6,
7, 8,9
18, 17, 16,
15, 14, 13,
12, 11
19
10
20
SYMBOL
DIR
A1 to A8
B1 to B8
NAME AND FUNCTION
Directional Control
Data Inputs/Outputs
Data Inputs/Outputs
Table 3: Truth Table
X : Don‘t Care
Z : High Impedance
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
I/O
I
IK
I
O
I
OK
I
CC
or I
GND
DC V
CC
or Ground Current
Storage Temperature
T
stg
T
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
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INPUTS
FUNCTION
OUTPUT
A=B
B=A
Z
G
L
L
H
DIR
L
H
X
A BUS
B BUS
OUTPUT
INPUT
Z
INPUT
OUTPUT
Z
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7
DC Bus I/O Voltage (DIR, G)
DC Bus I/O Voltage
DC Input Diode Current
DC Output Current
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
V
V
mA
mA
mA
°C
°C
DC Output Diode Current
±
400
300
mA
-65 to +150
Lead Temperature (10 sec)
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Parameter
Value
Unit
V
V
V
°C
ns/V
Supply Voltage (note 1)
Input Voltage (DIR, G)
DC Bus I/O Voltage
Operating Temperature
Input Rise and Fall Time V
CC
= 3.0V (note 2)
2 to 3.6
0 to V
CC
0 to V
CC
-55 to 125
0 to 10
G
GND
V
CC
Output Enable Input
Ground (0V)
Positive Supply Voltage
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
2/12
74LVQ245
Table 6: DC Specifications
Test Condition
Symbol
Parameter
V
CC
(V)
T
A
= 25°C
Min.
2.0
0.8
I
O
=-50
µA
3.0
I
O
=-12 mA
I
O
=-24 mA
I
O
=50
µA
I
O
=12 mA
I
O
=24 mA
2.9
2.58
2.99
2.9
2.48
2.2
Typ.
Max.
Value
-40 to 85°C
Min.
2.0
0.8
2.9
2.48
2.2
V
Max.
-55 to 125°C
Min.
2.0
0.8
Max.
V
V
Unit
V
IH
V
IL
V
OH
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
Table 7: Dynamic Switching Characteristics
O
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
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Pr
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V
OL
Low Level Output
Voltage
0.002
0
0.1
0.1
0.1
3.0
0.36
0.44
0.44
V
0.55
±
1
0.55
±
1
I
I
I
OZ
I
CC
Input Leakage
Current
High Impedance
Output Leakage
Current
Quiescent Supply
Current
3.6
3.6
3.6
3.6
V
I
= V
CC
or GND
±
0.1
µA
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
V
I
= V
CC
or GND
±
0.3
4
±
3
40
±
10
40
µA
µA
I
OLD
I
OHD
Dynamic Output
Current (note 1, 2)
V
OLD
= 0.8 V max
V
OHD
= 2 V min
36
25
mA
-25
-25
mA
Test Condition
Value
Symbol
Parameter
V
CC
(V)
3.3
3.3
T
A
= 25°C
Typ.
0.5
-40 to 85°C
-55 to 125°C
Min.
Max.
Unit
Min.
Max.
0.8
Min.
Max.
V
OLP
V
OLV
V
IHD
V
ILD
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input
(note 1, 3)
Dynamic Low
Voltage Input
(note 1, 3)
-0.8
2
-0.5
V
V
C
L
= 50 pF
3.3
0.8
V
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
3.0 to
3.6
3/12
74LVQ245
Table 8: AC Electrical Characteristics
(C
L
= 50 pF, R
L
= 500
Ω,
Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
T
A
= 25°C
Min.
Typ.
6.7
5.7
9.3
7.5
7.5
6.6
0.5
0.5
Max.
11.0
9.0
15.0
12.0
12.0
1.0
1.0
10.0
Value
-40 to 85°C
Min.
Max.
13.0
10.5
17.5
14.0
14.0
11.5
1.0
1.0
-55 to 125°C
Min.
Max.
15.0
12.0
20.0
16.0
16.0
1.0
1.0
13.0
ns
ns
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time
t
PZL
t
PZH
Output Enable
Time
t
PLZ
t
PHZ
Output Disable
Time
t
OSLH
t
OSHL
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= |t
PLHm
- t
PLHn
|, t
OSHL
= |t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
±
0.3V
Table 9: Capacitive Characteristics
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per circuit)
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Pr
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Output To Output
Skew Time
(note1, 2)
ns
Test Condition
Value
Symbol
Parameter
V
CC
(V)
3.3
T
A
= 25°C
Typ.
5
-40 to 85°C
-55 to 125°C
Min.
Max.
Unit
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
I/O Capacitance
pF
C
I/O
3.3
3.3
10
pF
pF
C
PD
Power Dissipation
Capacitance (note
1)
f
IN
= 10MHz
20
4/12
74LVQ245
Figure 3: Test Circuit
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500Ω or equivalent
R
T
= Z
OUT
of pulse generator (typically 50Ω)
Figure 4: Waveform - Propagation Delays
(f=1MHz; 50% duty cycle)
O
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(s
P
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Pr
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) -
ol
(s
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ct
O
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-
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r
(
P
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du
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Pr
b
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TEST
SWITCH
Open
2V
CC
Open
5/12
测试/测量
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