19-2130; Rev 2; 11/10
IT
TION K
VALUA BLE
E
AVAILA
10-Bit Bus LVDS Deserializers
Features
o
Stand-Alone Deserializer (vs. SerDes) Ideal for
Unidirectional Links
o
Automatic Clock Recovery
o
Allow Hot Insertion and Synchronization Without
System Interruption
o
BLVDS Serial Input Rated for Point-to-Point and
Bus Applications
o
Fast Pseudorandom Lock
o
Wide Reference Clock Input Range
16MHz to 45MHz (MAX9206)
40MHz to 60MHz (MAX9208)
o
High 720ps (p-p) Jitter Tolerance (MAX9206)
o
Low 30mA Supply Current (MAX9206 at 16MHz)
o
10-Bit Parallel LVCMOS/LVTTL Output
o
Up to 600Mbps Throughput (MAX9208)
o
Programmable Output Strobe Edge
o
Pin Compatible to DS92LV1212A and
DS92LV1224
General Description
The MAX9206/MAX9208 deserializers transform a high-
speed serial bus low-voltage differential signaling
(BLVDS) data stream into 10-bit-wide parallel LVCMOS/
LVTTL data and clock. The deserializers pair with seri-
alizers such as the MAX9205/MAX9207, which gener-
ate a serial BLVDS signal from 10-bit-wide parallel
data. The serializer/deserializer combination reduces
interconnect, simplifies PCB layout, and reduces board
size.
The MAX9206/MAX9208 receive serial data at
450Mbps and 600Mbps, respectively, over board
traces or twisted-pair cables. These devices combine
frequency lock, bit lock, and frame lock to produce a
parallel-rate clock and word-aligned 10-bit data.
Serialization eliminates parallel bus clock-to-data and
data-to-data skew.
A power-down mode reduces typical supply current to
less than 600µA. Upon power-up (applying power or
driving
PWRDN
high), the MAX9206/MAX9208 estab-
lish lock after receiving synchronization signals or serial
data from the MAX9205/MAX9207. An output enable
allows the outputs to be disabled, putting the parallel
data outputs and recovered output clock into a high-
impedance state without losing lock.
The MAX9206/MAX9208 operate from a single +3.3V
supply and are specified for operation from -40°C to
+85°C. The MAX9206/MAX9208 are available in 28-pin
SSOP packages.
MAX9206/MAX9208
Ordering Information
PART
MAX9206EAI+
MAX9208EAI+
TEMP
RANGE
PIN-
PACKAGE
REF CLOCK
RANGE
(MHz)
16 to 40
16 to 40
40 to 66
Applications
Cellular Phone Base
Stations
Add/Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches and
Routers
Backplane Interconnect
-40°C to +85°C 28 SSOP
-40°C to +85°C 28 SSOP
MAX9206EAI/V+ -40°C to +85°C 28 SSOP
+Denotes
a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
PARALLEL-TO-SERIAL
OUT+
100Ω
OUT-
PCB OR TWISTED PAIR
EN
PWRDN
MAX9205
MAX9207
MAX9206
MAX9208
PLL
RI+
100Ω
RI-
SERIAL-TO-PARALLEL
BUS
LVDS
OUTPUT LATCH
INPUT LATCH
10
IN_
TCLK_R/F
TCLK
10
ROUT_
REFCLK
PLL
TIMING AND
CONTROL
TIMING AND
CONTROL
CLOCK
RECOVERY
REN
LOCK
RCLK
RCLK_R/F
SYNC 1
SYNC 2
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
10-Bit Bus LVDS Deserializers
MAX9206/MAX9208
ABSOLUTE MAXIMUM RATINGS
AVCC, DVCC to AGND, DGND................................-0.3V to +4V
RI+, RI- to AGND, DGND .........................................-0.3V to +4V
All Other Pins to DGND ..............................-0.3V to DV
CC
+ 0.3V
ROUT_ Short-Circuit Duration (Note 1) ......................Continuous
Continuous Power Dissipation (T
A
= +70°C)
28-Pin SSOP (derate 9.5mW/°C above +70°C) ..........762mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Rating (Human Body Model, RI+, RI-) .........................±8kV
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
AVCC
= V
DVCC
= +3.0V to +3.6V, differential input voltage
|
V
ID
|
= 0.1V to 1.2V, common-mode voltage V
CM
=
|
V
ID
/2
|
to 2.4V
-
|
V
ID
/2
|
, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
AVCC
= V
DVCC
= +3.3V, V
CM
= 1.1V,
|
V
ID
|
= 0.2V,
T
A
= +25°C.) (Notes 2, 3)
PARAMETER
POWER SUPPLY
C
L
= 15pF,
worst-case
pattern,
Figure 1
PWRDWN
= low
2.0
0
V
IN
= 0V, V
AVCC
, or V
DVCC
I
OH
= -5mA
I
OL
= 5mA
V
ROUT_
= 0V
PWRDN
= low, V
ROUT_
= V
RCLK
= V
LOCK
= 0V, V
AVCC
, or V
DVCC
-15
2.2
0
-15
-1
2.9
0.33
-38
MAX9206
MAX9208
16MHz
45MHz
40MHz
60MHz
30
57
55
80
45
75
75
100
1
V
CC
0.8
15
V
CC
0.5
-85
1
mA
V
V
μA
V
V
mA
μA
mA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current
I
CC
Power-Down Supply Current
High-Level Input Voltage
Low-Level Input Voltage
Input Current
High-Level Output Voltage
Low-Level Output Voltage
Output Short-Circuit Current
Output High-Impedance Current
BLVDS SERIAL INPUT (RI+, RI-)
Differential Input High
Differential Input Low Threshold
Input Current
Power-Off Input Current
Input Resistor 1
Input Resistor 2
I
CCX
V
IH
V
IL
I
IN
V
OH
V
OL
I
OS
I
OZ
LVCMOS/LVTTL LOGIC INPUTS (REN, REFCLK, RCLK_R/F,
PWRDN)
LVCMOS/LVTTL LOGIC OUTPUTS (ROUT_, RCLK,
LOCK)
V
TH
V
TL
I
RI+
, I
RI-
I
RI+OFF
,
I
RI-OFF
R
IN1
R
IN2
0.1V
0.1V
|V
ID
|
|V
ID
|
0.45V
0.6V
0.45V, V
AVCC
= V
DVCC
= 0V
0.45V
<
|V
ID
|
-100
-64
-82
-64
-82
4
150
9
-9
100
64
82
64
82
mV
mV
μA
μA
k
k
0.45V
<
|V
ID
| 0.6V, V
AVCC
= V
DVCC
= 0V
V
AVCC
= V
DVCC
= 3.6V or 0V, Figure 2
V
AVCC
= V
DVCC
= 3.6V or 0V, Figure 2
2
_______________________________________________________________________________________
10-Bit Bus LVDS Deserializers
MAX9206/MAX9208
AC ELECTRICAL CHARACTERISTICS
(V
AVCC
= V
DVCC
= +3.0V to +3.6V, C
L
= 15pF, differential input voltage
|
V
ID
|
= 0.15V to 1.2V, common-mode voltage V
CM
=
|
V
ID
/2
|
to 2.4V -
|
V
ID
/2
|
, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
AVCC
= V
DVCC
= +3.3V, V
CM
= 1.1V,
|
V
ID
|
=
0.2V, T
A
= +25°C.) (Notes 4, 5)
PARAMETER
SYMBOL
MAX9206
MAX9208
MAX9206
MAX9208
CONDITIONS
MIN
16
40
-200
22.222
16.666
30
50
3
MAX9206
MAX9208
Figure 3
Figure 3
MAX9206, 45MHz
Deserializer Delay
t
DD
Figure 4
MAX9208, 60MHz
ROUT_ Data Valid Before RCLK
ROUT_ Data Valid After RCLK
RCLK Duty Cycle
OUTPUT High-to-High
Impedance Delay
OUTPUT Low-to-High
Impedance Delay
OUTPUT High-Impedance to
High-State Delay
OUTPUT High-Impedance to
Low-State Delay
PLL Lock Time (from
PWRDN
Transition High)
t
ROS
t
ROH
t
RDC
t
HZR
t
LZR
t
ZHR
t
ZLR
C
L
= 5pF, Figure 6
C
L
= 5pF, Figure 6
C
L
= 5pF, Figure 6
C
L
= 5pF, Figure 6
Sync patterns at input; supply and
REFCLK stable; measured from
PWRDN
transition high to
LOCK
transition low; Figure 7
Figure 5
Figure 5
22.222
16.666
1.5
2
TYP
MAX
45
60
200
62.500
25
70
6
62.500
25
3
3
UNITS
REFERENCE CLOCK TIMING REQUIREMENTS (REFCLK)
REFCLK Frequency
REFCLK Frequency Variation
REFCLK Period
REFCLK Duty Cycle
REFCLK Input Transition Time
SWITCHING CHARACTERISTICS
Recovered Clock (RCLK)
Period (Note 6)
Low-to-High Transition Time
High-to-Low Transition Time
t
RCP
t
CLH
t
CHL
ns
ns
ns
f
RFF
RFFV
t
RFCP
RFDC
t
RFTT
MHz
ppm
ns
%
ns
1.75 x t
RCP
1.75 x t
RCP
1.75 x t
RCP
+2
+ 3.3
+ 6.5
1.75 x t
RCP
1.75 x t
RCP
1.75 x t
RCP
+ 1.1
+ 3.3
+ 5.6
0.4 x t
RCP
0.4 x t
RCP
43
0.5 x t
RCP
0.5 x t
RCP
50
57
8
8
6
6
ns
ns
ns
%
ns
ns
ns
ns
t
DSR1
(2048 + 42)
x t
RFCP
ns
_______________________________________________________________________________________
3
10-Bit Bus LVDS Deserializers
MAX9206/MAX9208
AC ELECTRICAL CHARACTERISTICS (continued)
(V
AVCC
= V
DVCC
= +3.0V to +3.6V, C
L
= 15pF, differential input voltage
|
V
ID
|
= 0.15V to 1.2V, common-mode voltage V
CM
=
|
V
ID
/2
|
to 2.4V -
|
V
ID
/2
|
, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
AVCC
= V
DVCC
= +3.3V, V
CM
= 1.1V,
|
V
ID
|
=
0.2V, T
A
= +25°C.) (Notes 4, 5)
PARAMETER
PLL Lock Time (from Start of
Sync Patterns)
LOCK
High-Z to High-State
Delay
SYMBOL
CONDITIONS
PLL locked to stable REFCLK; supply
stable; static input; measured from
start of sync patterns at input to
LOCK
transition low; Figure 8
Figure 7
MAX9206
Input Jitter Tolerance
t
JT
Figure 9
MAX9208
16MHz
45MHz
40MHz
60MHz
1300
720
720
320
ps
MIN
TYP
MAX
UNITS
t
DSR2
42 x t
RFCP
ns
t
ZHLK
30
ns
Note 1:
Short one output at a time. Do not exceed the Absolute Maximum continuous power dissipation.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative. Voltages are referenced to ground
except V
TH
, V
TL
, and V
ID
, which are differential input voltages.
Note 3:
DC parameters are production tested at T
A
= +25°C and guaranteed by design and characterization over operating temper-
ature range.
Note 4:
AC parameters guaranteed by design and characterization.
Note 5:
C
L
includes scope probe and test jig capacitance.
Note 6:
t
RCP
is determined by the period of TCLK, which is the reference clock of the serializer driving the deserializer. The frequen-
cy of TCLK must be within ±400ppm of the REFCLK frequency.
4
_______________________________________________________________________________________
10-Bit Bus LVDS Deserializers
Pin Description
PIN
1, 12, 13
2
3
4, 11
5
6
7
8
9
10
14, 20,
22
15–19,
24–28
21, 23
NAME
AGND
RCLK_R/F
REFCLK
AVCC
RI+
RI-
PWRDN
REN
RCLK
LOCK
DGND
ROUT9–
ROUT0
DVCC
Analog Ground
Recovered Clock Strobe Edge Select. LVTTL/LVCMOS level input. Drive RCLK_ R/F high to strobe
ROUT_ on the rising edge of RCLK. Drive RCLK_R/F low to strobe ROUT_ on the falling edge of
RCLK.
PLL Reference Clock. LVTTL/LVCMOS level input.
Analog Power Supply. Bypass AVCC with a 0.1μF and a 0.001μF capacitor to AGND.
Serial Data Input. Noninverting BLVDS differential input.
Serial Data Input. Inverting BLVDS differential input.
Power Down. LVTTL/LVCMOS level input. Drive
PWRDN
low to stop the PLL and put ROUT_,
LOCK,
and RCLK in high impedance.
Output Enable. LVTTL/LVCMOS level input. Drive REN low to put ROUT_ and RCLK in high
impedance.
LOCK
remains active, indicating the status of the serial input.
Recovered Clock. LVTTL/LVCMOS level output. Use RCLK to strobe ROUT_.
Lock Indicator. LVTTL/LVCMOS level output.
LOCK
goes low when the PLL has achieved frequency
and phase lock to the serial input, and the framing bits have been identified.
Digital Ground
Parallel Output Data. LVTTL/LVCMOS level outputs. ROUT_ is valid on the second selected strobe
edge of RCLK after
LOCK
goes low.
Digital Power Supply. Bypass DVCC with a 0.1μF and a 0.001μF capacitor to DGND.
FUNCTION
MAX9206/MAX9208
Test Circuits/Timing Diagrams
START
BIT
RI
0
1
2
3
4
5
6
7
8
9
START
BIT
END
BIT
0
1
2
3
4
5
6
7
8
9
START
BIT
0
1
2
END
BIT
T
DD
RCLK
ODD
ROUT
RCLK_R/F = HIGH
EVEN
ROUT
Figure 1. Worst-Case I
CC
Test Pattern
_______________________________________________________________________________________
5
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