74HC4024
7-stage binary ripple counter
Rev. 6 — 23 August 2012
Product data sheet
1. General description
The 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the 4024
of the 4000B series. The 74HC4024 is specified in compliance with JEDEC
standard no. 7A.
The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to
Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears
all counter stages and forces all outputs LOW, independent of the state of CP. Each
counter stage is a static toggle flip-flop.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features and benefits
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from
40 C
to +80
C
and from
40 C
to +125
C.
3. Applications
Frequency dividing circuits
Time delay circuits.
NXP Semiconductors
74HC4024
7-stage binary ripple counter
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC4024N
74HC4024D
74HC4024DB
74HC4024PW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
DIP14
SO14
SSOP14
TSSOP14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
Version
SOT27-1
SOT108-1
SOT337-1
SOT402-1
Type number
5. Functional diagram
Q6 3
Q5 4
7-STAGE
COUNTER
Q0
1
CP
Q1
Q2
Q3
2
MR
Q4
Q5
Q6
001aab906
Q4 5
Q3 6
CTR7
0
1
+
CT
2
CT = 0
12
11
9
6
5
4
3
12
11
9
6
5
4
Q2 9
Q1 11
Q0 12
CP
1
MR
2
001aab908
6
001aab907
3
Fig 1.
Logic symbol
Fig 2.
Functional diagram
Fig 3.
IEC logic symbol
Q
CP
T
FF
1
T
Q
RD
MR
RD
FF
2
Q
T
Q
RD
FF
3
Q
T
Q
RD
FF
4
Q
T
Q
RD
FF
5
Q
T
Q
RD
FF
6
Q
T
Q
RD
FF
7
Q
Q
Q0
Q1
Q2
Q3
Q4
Q5
Q6
001aab909
Fig 4.
74HC4024
Logic diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
2 of 19
NXP Semiconductors
74HC4024
7-stage binary ripple counter
6. Pinning information
6.1 Pinning
74HC4024
CP
MR
Q6
Q5
Q4
Q3
GND
1
2
3
4
5
6
7
001aab905
14 V
CC
13 n.c.
12 Q0
11 Q1
10 n.c.
9
8
Q2
n.c.
Fig 5.
Pin configuration
6.2 Pin description
Table 2.
Symbol
CP
MR
Q6, Q5, Q4, Q3, Q2, Q2, Q1, Q0
GND
n.c.
V
CC
Pin description
Pin
1
2
3, 4, 5, 6, 9, 11, 12
7
8, 10, 13
14
Description
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
parallel output
ground (0 V)
not connected
positive supply voltage
7. Functional description
Table 3.
Input
MR
H
L
CP
X
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH clock transition;
=
HIGH-to-LOW clock transition.
Function table
[1]
Output
Qn
L
no change
count
74HC4024
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
3 of 19
NXP Semiconductors
74HC4024
7-stage binary ripple counter
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP14 package
SO14 package
SSOP14 and TSSOP14 package
[1]
[2]
[3]
For DIP16 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
For (T)SSOP16 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
[1]
[2]
[3]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to V
CC
+ 0.5 V
Min
0.5
-
-
-
-
50
65
-
-
-
Max
+7
20
20
25
50
-
+150
750
500
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
mW
9. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
input transition rise and fall
rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
T
amb
ambient temperature
Conditions
Min
2.0
0
0
-
-
-
40
Typ
5.0
-
-
-
1.67
-
-
Max
6.0
V
CC
V
CC
625
139
83
+125
Unit
V
V
V
ns/V
ns/V
ns/V
C
74HC4024
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
4 of 19
NXP Semiconductors
74HC4024
7-stage binary ripple counter
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
T
amb
= 25
C
V
IH
HIGH-level input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
4
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
V
IH
input leakage current
supply current
input capacitance
HIGH-level input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
4
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
I
= V
CC
or GND; V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A; V
CC
= 6.0 V
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
-
0
0
0
0.15
0.16
-
-
3.5
-
-
-
-
-
-
0.1
0.1
0.1
0.26
0.26
0.1
8.0
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
A
A
pF
V
V
V
V
V
V
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Parameter
Conditions
Min
Typ
Max
Unit
T
amb
=
40 C
to +85
C
74HC4024
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
5 of 19
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