STFI10NK60Z
N-channel 600 V, 0.65
Ω
10 A, Zener-protected SuperMESH™
,
Power MOSFET in I²PAKFP package
Datasheet — production data
Features
Type
STFI10NK60Z
■
V
DSS
600 V
R
DS(on)
max
I
D
P
TOT
35 W
< 0.75
Ω
10 A
Fully insulated and low profile package with
increased creepage path from pin to heatsink
plate
Extremely high dv/dt capability
100% avalanche tested
Gate charge minimized
1
2
3
■
■
■
I²PAKFP
(TO-281)
Applications
■
Switching applications
Figure 1.
Internal schematic diagram
D(2)
Description
This device is an N-channel Zener-protected
Power MOSFET developed using
STMicroelectronics' SuperMESH™ technology,
achieved through optimization of ST's well-
established strip-based PowerMESH™ layout. In
addition to a significant reduction in on-
resistance, this device is designed to ensure a
high level of dv/dt capability for the most
demanding applications.
G(1)
S(3)
AM01476v1
Table 1.
Device summary
Marking
10NK60Z
Package
I
2
PAKFP
(TO-281)
Packaging
Tube
Order code
STFI10NK60Z
March 2012
This is information on a product in full production.
Doc ID 018968 Rev 3
1/13
www.st.com
13
Contents
STFI10NK60Z
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
........................... 6
3
4
5
Test circuits
.............................................. 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
Doc ID 018968 Rev 3
STFI10NK60Z
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
V
DS
V
GS
I
D
I
D
I
DM (2)
P
TOT
ESD
dv/dt
(3)
V
ISO
T
j
T
stg
2.
Absolute maximum ratings
Parameter
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Gate-source human body model (R=1,5 kΩ C=100 pF)
,
Peak diode recovery voltage slope
Insulation withstand voltage (RMS) from all three
leads
to external heat sink (t=1 s;T
C
=25 °C)
Operating junction temperature
Storage temperature
Value
600
± 30
10
(1)
5.7
(1)
36
(1)
35
4
4.5
2500
-55 to 150
Unit
V
V
A
A
A
W
kV
V/ns
V
°C
1. Limited by maximum junction temperature
Pulse width limited by safe operating area
3. I
SD
< 10A, di/dt < 200A/µs, V
DD
=80% V
(BR)DSS
Table 3.
Symbol
R
thj-case
R
thj-amb
Thermal data
Parameter
Thermal resistance junction-case Max
Thermal resistance junction-amb Max
Value
3.6
62.5
Unit
°C/W
°C/W
Table 4.
Symbol
I
AR
E
AS
1.
Avalanche characteristics
Parameter
Repetitive or non repetitive avalanche current
Single pulse avalanche energy
(starting Tj=25 °C, I
D
=I
AR
, V
DD
= 50 V)
Value
9
(1)
300
Unit
A
mJ
Limited by maximum junction temperature
Doc ID 018968 Rev 3
3/13
Electrical characteristics
STFI10NK60Z
2
Electrical characteristics
(Tcase = 25 °C unless otherwise specified).
Table 5.
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
On /off states
Parameter
Test conditions
Min.
600
1
50
±
10
Typ.
Max.
Unit
V
µA
µA
µA
V
Ω
Drain-source breakdown
I
D
= 250 µA
voltage, (V
GS
= 0)
Zero gate voltage drain
current (V
GS
= 0)
Gate body leakage
current (V
DS
= 0)
Gate threshold voltage
Static drain-source on
resistance
V
DS
= 600 V
V
DS
= 600 V, T
C
= 125 °C
V
GS
= ±20 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 4.5 A
3
3.75
0.65
4.5
0.75
Table 6.
Symbol
g
fs (1)
C
iss
C
oss
C
rss
C
oss eq(2)
Q
g
Q
gs
Q
gd
Dynamic
Parameter
Forward
transconductance
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent output
capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Test conditions
V
DS
=15 V, I
D
= 4.5 A
Min.
-
Typ.
7.8
1370
156
37
90
50
10
25
70
Max.
Unit
S
pF
pF
pF
pF
nC
nC
nC
V
DS
=25 V, f=1 MHz, V
GS
=0
-
V
GS
=0, V
DS
=0 to 480 V
V
DD
=480 V, I
D
= 8 A
V
GS
=10 V
(see Figure 16)
-
-
1. Pulsed: pulse duration = 300µs, duty cycle 1.5%
2. C
oss eq
. is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80%
Table 7.
Symbol
t
d(on)
t
r
t
d(off)
t
f
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
V
DD
=300 V, I
D
=4 A,
R
G
=4.7
Ω,
V
GS
=10 V
(see Figure 15)
V
DD
=300 V, I
D
=4 A,
R
G
=4.7
Ω,
V
GS
=10 V
(see Figure 15)
Min.
Typ.
20
20
55
30
Max Unit
ns
ns
ns
ns
-
-
-
-
4/13
Doc ID 018968 Rev 3
STFI10NK60Z
Electrical characteristics
Table 8.
Symbol
I
SD
I
SDM
(1)
Source drain diode
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
=10 A, V
GS
=0
I
SD
=8 A, di/dt = 100 A/µs,
V
DD
=40 V, Tj=150 °C
Test conditions
Min.
-
-
-
570
4.3
15
Typ.
Max. Unit
10
36
1.6
A
A
V
ns
µC
A
V
SD(2)
t
rr
Q
rr
I
RRM
2.
1. Pulse width limited by safe operating area
Pulsed: pulse duration = 300µs, duty cycle 1.5%
Table 9.
Symbol
V
(BR)GSO
Gate-source Zener diode
Parameter
Gate-source breakdown
voltage (I
D
=0)
Test conditions
I
GS
= ± 1 mA
Min.
30
Typ.
-
Max. Unit
V
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.
Doc ID 018968 Rev 3
5/13
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