VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8132
Features
• 2.488Gb/s 1:32 Demultiplexer
• SONET STS-48/SDH STM-16
• HSPECL Differential Serial Data and Clock
Inputs
• 32-Bit TTL Parallel Data Outputs with Odd/
Even Parity Check
• Frame Detect Synchronization
2.488Gb/s 1:32 SONET/SDH Demux
• 77.76, 51.84, and 38.88MHz TTL Clock Outputs
• Single 3.3V supply
• Loss of Clock Alarm
• Loss of Data Alarm
• 2.05W Max Power Dissipation
• 128-Pin PQFP Package
General Description
The VSC8132 demultiplexes a 2.488Gb/s HSPECL serial input datastream (DI+) to 32-bit wide, TTL
77.76Mb/s parallel data outputs D[31:0] for SONET/SDH applications. A 2.488GHz HSPECL input clock
(CLKI+) is used to time the incoming data and 3 TTL clock outputs, at frequencies of 77.76MHz, 51.84MHz,
and 38.88MHz, are generated for upstream devices (DATACLK78, CLK51, CLK38). Odd or even parity is per-
formed on the incoming high-speed data via the TTL Parity Select input (PARSEL), and a TTL Parity output
(PARITY) is provided to indicate parity of the input data. Frame Detect on the incoming data is controlled via
the Frame Detect Inhibit (OOFN) and Reset (RESET) TTL inputs. A frame detect monitors the incoming data
steam and screens for 2 bits in A1 byte out of the 8 bits and 2 bits of A2 byte out of the 8 bits. When a Frame
Detect occurs, a synchronization TTL output (SYNC) will be set. Alarm indicators are used to monitor the
activity of the clock and data with TTL compatible control inputs (ALMRESET) and outputs (DTALARM,
CKALARM).
Only a single 3.3V power supply is required for device operation. The VSC8132 is packaged in a ther-
mally-enhanced 128-pin, 14x20x2mm PQFP package.
VSC8132 Block DIagram
OOFN
RESET
PARSEL
Framing
and
Parity
DATA[3:0]
SYNC
PARITY
DI+
DI–
CLKI+
CLKI–
DTALARM
Alarms
ALMRESET
CKALARM
DATACLK78
1:32
Demux
Clock
Generation
CLK51
CLK38
G52250-0, Rev 3.1
12/7/00
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
2.488Gb/s 1:32 SONET/SDH Demux
VSC8132
Functional Description
High-Speed Clock and Data Interface
The incoming high-speed data and high-speed clock are received by high-speed inputs DI+ and CLKI+.
The inputs are internally biased to accommodate AC-coupling.
The data and clock inputs are internally terminated by a center-tapped resistor network. For differential
input DC-coupling, the network is terminated to the appropriate termination voltage,
V
TERM
providing a 50
Ω
to
V
TERM
termination for both true and complement inputs. For differential input AC-coupling, the network is ter-
minated to
V
TERM
via a blocking capacitor.
In most situations, these inputs will have high transition density and little DC offset. However, in cases
where this does not hold, direct DC connection is possible. All serial data and clock inputs have the same circuit
topology as shown in Figure 1. The reference voltage is created by a resistor divider as shown. If the input sig-
nal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be cen-
tered about this reference voltage and not exceed the maximum allowable amplitude. For single-ended, DC-
coupling operations, it is recommended that the user provides an external reference voltage which has better
temperature and power supply noise rejection than the on-chip resistor divider. The external reference should
have a nominal value equivalent to the common mode switch point of the DC-coupled signal, and can be con-
nected to either side of the differential gate.
Figure 1: High-Speed Clock and Data Inputs
Chip Boundary
V
CC
= 3.3V
1.65V
Z
0
C
IN
100nF
3kΩ
3kΩ
1.65V
C
AC
100nF
V
TERM
C
IN
100nF
50Ω
3kΩ
I
I
3kΩ
Z
0
50Ω
V
EE
= 0V
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52250-0, Rev 3.1
12/7/00
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8132
2.488Gb/s 1:32 SONET/SDH Demux
Low-Speed Data Interface
The 77.76Mb/s parallel data outputs D[31:0] are clocked out of the VSC8132 on the falling clock edge of
the 77.76MHz output clock (DATA78CLK). The data and clock are TTL levels. The MSB (D31) bit is the first
bit into the serial interface.
Parity Selection
The parity output bit (PARITY) is clocked out on the falling edge of the 77.76MHz clock (DATA78CLK).
This bit indicates the parity of the 32 bits of data along with the frame sync bit. The parity of the output is deter-
mined by the parity select input (PARSEL). When the parity select input is LOW, the output parity is odd. When
the parity select is HIGH, the output parity is even. The parity inputs and outputs are TTL levels. See Figure 2
for output timing relationship.
Framing Logic Interface
When a frame detect occurs and the frame detect inhibit input (OOFN) is set LOW, the frame detect output
(SYNC) is set HIGH on the negative edge of the 77.76MHz clock and on the 3rd set of four A2 bytes at the 32-
bit data output. The frame detect mechanism is inhibited when the frame detect inhibit (OOFN) input is set
HIGH. The frame detect output and frame detect inhibit are TTL levels.
NOTE: The 77.76MHz clock misses one clock cycle during a frame detect. This missed cycle occurs one
clock period before the Sync pulse is set HIGH (see Figure 4).
To use as a framer:
Step 1: Set OOFN LOW
Step 2:Wait for Sync pulse
Step 3:When Sync Pulse goes HIGH, set OOFN HIGH
Chip Reset
Chip reset (RESET) will reset the framing logic so that no frame detection barrel shifting is performed.
Therefore, if the frame detect inhibit input is set high, the chip will act as a simple demux after reset. The reset
should be set high for 16 clock cycles of the high speed clock input. The chip reset is a TTL level.
Alarm Logic Interface
The Loss of Clock (CKALARM) and Loss of Data (DTALARM) alarms monitor the activity of the clock
and data. The Alarm Reset (ALMRESET) input controls the alarm activity. Polling of the alarms signals are ini-
tiated by toggling the Alarm Reset input HIGH and then LOW one time. To reset both alarm outputs, the Alarm
Reset should be toggled HIGH to LOW two times. All alarm logic interface signals are TTL levels.
Supplies
The VSC8132 is specified as a HSPECL/TTL device with a single positive 3.3V supply. Normal operation
is to have V
CC
= +3.3V and V
EE
= ground. Should the user desire to use the device in a ECL environment with
a negative 3.3V supply, V
CC
will be ground and V
EE
will be -3.3V. If used with V
EE
tied to -3.3V, the TTL out-
put signals are still referenced to V
EE
.
G52250-0, Rev 3.1
12/7/00
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
2.488Gb/s 1:32 SONET/SDH Demux
VSC8132
Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is
recommended that the V
CC
power supply be decoupled using a 0.1
µ
F and 0.01
µ
F capacitor placed in parallel
on each V
CC
power supply pin as close to the package as possible. If room permits, a 0.001
µ
F capacitor should
also be placed in parallel with the 0.1
µ
F and 0.01
µ
F capacitors mentioned above. Recommended capacitors are
low-inductance ceramic SMT X7R devices. For the 0.1
µ
F capacitor, a 0603 package should be used. The
0.01
µ
F and 0.001
µ
F capacitors can be either 0603 or 0402 packages.
For low frequency decoupling, 47
µ
F tantalum, low-inductance SMT caps should be sprinkled over the
board’s main +3.3V power supply and placed close to the C-L-C pi filter.
If the device is being used in an ECL environment with a -3.3V supply, all references to decoupling V
CC
must be changed to V
EE
, and all references to decoupling 3.3V must be changed to -3.3V.
AC Characteristics
Figure 2: Output Timing
t
PD1
t
PD2
78MHz CLK
78MHz DATA
SYNC PULSE
PARITY
Figure 3: Data Output Timing
t
SERSU
DI+
Differential Serial Data Input
t
SERHO
D0
LSB
Time
CLKI+
Differential Clock Input
D31
MSB
NOTE: Bit 31 (MSB) is received first, Bit 0 (LSB) is received last.
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52250-0, Rev 3.1
12/7/00
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8132
Missed Clock
Pulse
(1)
CLK78 (Out)
(1)
2.488Gb/s 1:32 SONET/SDH Demux
Figure 4: Framing Sequence
Approximately <110µs
SYNC PULSE (Out)
OOFN (In)
(asynchronous)
Set HIGH, less than 110µs
after SYNC goes HIGH
NOTE: (1) No missing clock pulse for CLK78 when VSC8132 is working as a dumb demux.
Once frame occurs and OOFN is set HIGH, the no framing will occur until
OOFN is set LOW again. The VSC8132 will remain framed with SONET frame.
Table 1: AC Characteristics
Parameters
t
DATApd
t
CLKRpd
t
CLKFpd
t
DEDGE
t
CLKEDGE
t
CONEDGE
t
SERSU
t
SERHO
f
MAX
t
CLK38Rpd
t
CLK38Fpd
t
CLK51Rpd
t
CLK51Fpd
t
PD1
, t
PD2
Description
Data Valid From Falling Edge of 77.76MHz
High-speed Clock Rising Edge to 77.76MHz
Clock Rising Edge
High-Speed Clock Rising Edge to 77.76MHz
Clock Falling Edge
D[0:31] Edge Rate (10%-90%)
77.76, 51.84, 38.88MHz Edge Rates (10%-90%)
Control Signals (SYNC, PARITY, DTALARM,
and CKALARM) Edge Rate (10%-90%)
DI+ Setup Time with Respect to Falling Edge of
CLKI+
DI+ Hold Time with Respect to Falling Edge of
CLKI+
Demux Input Maximum Clock Frequency
High-Speed Clock Rising Edge to 38.88MHz
Clock Rising Edge.
High-Speed Clock Rising Edge to 38.88MHz
Clock Falling Edge
High-Speed Clock Rising Edge to 51.84MHz
Clock Rising Edge
High-Speed Clock Rising Edge to 51.84MHz
Clock Falling Edge
Data Invalid Window
Min
230
2.5
2.3
-
-
-
100
75
-
2.0
2.0
2.0
2.0
0, 230
Typ
Max
1250
8.0
7.1
2.0
2.0
2.0
-
-
2.9
6.3
5.9
6.0
5.9
0, 1250
Units
ps
ns
ns
ns
ns
ns
ps
ps
GHz
ns
ns
ns
ns
ps
Conditions
External load = 5pf
External load = 5pf
External load = 5pf
External load = 5pf
External load = 5pf
External load = 5pf
See Figure 3
See Figure 3
External load = 5pf
External load = 5pf
External load = 5pf
External load = 5pf
G52250-0, Rev 3.1
12/7/00
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 5
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