74LVU04
Hex unbuffered inverter
Rev. 7 — 18 September 2014
Product data sheet
1. General description
The 74LVU04 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HCU04.
The 74LVU04 is a general purpose hex inverter. Each of the six inverters is a single stage
with unbuffered outputs.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
C
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Applications
Linear amplifier
Crystal oscillator
Astable multivibrator
NXP Semiconductors
74LVU04
Hex unbuffered inverter
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVU04N
74LVU04D
74LVU04DB
74LVU04PW
74LVU04BQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
DIP14
SO14
SSOP14
TSSOP14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT27-1
SOT108-1
SOT337-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
5. Functional diagram
V
CC
V
CC
V
CC
100
Ω
170
Ω
nA
nY
001aah110
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Circuit diagram (one
inverter)
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
2 of 20
NXP Semiconductors
74LVU04
Hex unbuffered inverter
6. Pinning information
6.1 Pinning
74LVU04
terminal 1
index area
14 V
CC
13 6A
12 6Y
11 5A
V
CC(1)
7
8
10 5Y
9
GND
4Y
4A
1A
2
3
4
5
6
1
1Y
14 V
CC
13 6A
12 6Y
11 5A
10 5Y
9
8
001aah108
74LVU04
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
2A
2Y
3A
3Y
4A
4Y
001aah109
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig 4.
Pin configuration DIP14, SO14 and (T)SSOP14
Fig 5.
Pin configuration DHVQFN14
6.2 Pin description
Table 2.
Symbol
1A
1Y
2A
2Y
3A
3Y
GND
4Y
4A
5Y
5A
6Y
6A
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input
data output
data input
data output
data input
data output
ground (0 V)
data output
data input
data output
data input
data output
data input
supply voltage
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
3 of 20
NXP Semiconductors
74LVU04
Hex unbuffered inverter
7. Functional description
Table 3.
Input nA
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
Function table
[1]
Output nY
H
L
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
DIP14 package
SO14 package
(T)SSOP14 package
DHVQFN14 package
[1]
[2]
[3]
[4]
[5]
[2]
[3]
[4]
[5]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
Min
0.5
-
-
-
-
50
65
-
-
-
-
Max
+7.0
20
50
25
50
-
+150
750
500
500
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 12 mW/K above 70
C.
P
tot
derates linearly with 8 mW/K above 70
C.
P
tot
derates linearly with 5.5 mW/K above 60
C.
P
tot
derates linearly with 4.5 mW/K above 60
C.
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
4 of 20
NXP Semiconductors
74LVU04
Hex unbuffered inverter
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
T
amb
t/V
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 3.6 V to 5.5 V
[1]
Conditions
[1]
Min
1.0
0
0
40
-
-
-
-
Typ
3.3
-
-
+25
-
-
-
-
Max
5.5
V
CC
V
CC
+125
500
200
100
50
Unit
V
V
V
C
ns/V
ns/V
ns/V
ns/V
The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to function down to
V
CC
= 1.0 V (with input levels GND or V
CC
).
10. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
100 A;
V
CC
= 1.2 V
I
O
=
100 A;
V
CC
= 2.0 V
I
O
=
100 A;
V
CC
= 2.7 V
I
O
=
100 A;
V
CC
= 3.0 V
I
O
=
100 A;
V
CC
= 4.5 V
I
O
=
6
mA; V
CC
= 3.0 V
I
O
=
12
mA; V
CC
= 4.5 V
-
1.8
2.5
2.8
4.3
2.4
3.6
1.2
2.0
2.7
3.0
4.5
2.82
4.2
-
-
-
-
-
-
-
-
1.8
2.5
2.8
4.3
2.2
3.5
-
-
-
-
-
-
-
V
V
V
V
V
V
V
40 C
to +85
C
Min
1.0
1.6
2.4
0.8V
CC
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.2
0.4
0.5
0.2V
CC
40 C
to +125
C
Unit
Min
1.0
1.6
2.4
0.8V
CC
-
-
-
-
Max
-
-
-
-
0.2
0.4
0.5
V
V
V
V
V
V
V
0.2V
CC
V
74LVU04
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 18 September 2014
5 of 20
NXP MCU
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