CY7C1339G
4-Mbit (128K × 32) Pipelined Sync SRAM
4-Mbit (128K × 32) Pipelined Sync SRAM
Features
■
■
■
■
■
Functional Description
The CY7C1339G SRAM integrates 128K × 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE
1
), depth-expansion
chip enables (CE
2
and CE
3
), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW
[A:D]
, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as controlled
by the byte write control inputs. GW when active LOW causes all
bytes to be written.
The CY7C1339G operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click
here.
Registered inputs and outputs for pipelined operation
128K × 32 common I/O architecture
3.3 V core power supply (V
DD
)
2.5 V/3.3 V I/O power supply (V
DDQ
)
Fast clock-to-output times
❐
4.0 ns (for 133-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Available in Pb-free 100-pin TQFP package
“ZZ” sleep mode option
■
■
■
■
■
■
■
Logic Block Diagram
A 0, A 1, A
A DDRESS
REGISTER
2
A
[1:0]
M ODE
A DV
CLK
Q1
A DSC
A DSP
BW
D
DQ
D
BYTE
W RITE REGISTER
DQ
C
BYTE
W RITE REGISTER
DQ
B
BYTE
W RITE REGISTER
DQ
A
BYTE
W RITE REGISTER
BURST
COUNTER
CLR
A ND
Q0
LOGIC
DQ
D
BYTE
W RITE DRIVER
DQ
C
BYTE
W RITE DRIVER
DQ
B
BYTE
W RITE DRIVER
DQ
A
BYTE
W RITE DRIVER
BW
C
M EM ORY
A RRA Y
SENSE
A M PS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
BW
B
BW
A
BW E
GW
CE
1
CE
2
CE
3
OE
ENA BLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Errata:
For information on silicon errata, see
"Errata"
on page 20. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05520 Rev. *R
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 8, 2016
CY7C1339G
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Partial Truth Table for Read/Write .................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Errata ............................................................................... 20
Part Numbers Affected .............................................. 20
Product Status ........................................................... 20
Ram9 Sync ZZ Pin Issues Errata Summary .............. 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC®Solutions ....................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Document Number: 38-05520 Rev. *R
Page 2 of 23
CY7C1339G
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
133 MHz
4.0
225
40
Unit
ns
mA
mA
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
[1]
A
A
CE
1
CE
2
BW
D
BW
C
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
DQ
C
DQ
C
V
DDQ
V
SSQ
DQ
C
DQ
C
DQ
C
DQ
C
V
SSQ
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SSQ
DQ
D
DQ
D
DQ
D
DQ
D
V
SSQ
V
DDQ
DQ
D
DQ
D
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
BYTE C
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1339G
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
NC
BYTE B
BYTE A
Note
1. Errata:
The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see
"Errata"
on page 20.
Document Number: 38-05520 Rev. *R
MODE
A
A
A
A
A
1
A
0
NC/72M
NC/36M
V
SS
V
DD
NC/18M
NC/9M
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 3 of 23
CY7C1339G
Pin Definitions
Name
A
0
, A
1
, A
I/O
Description
Input-
Address inputs used to select one of the 128K address locations.
Sampled at the rising edge of the
synchronous CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A1:A0 are fed to the
two-bit counter.
BW
A
, BW
B
,
Input-
Byte write select inputs, active LOW.
Qualified with BWE to conduct byte writes to the SRAM. Sampled
BW
C
, BW
D
synchronous on the rising edge of CLK.
GW
BWE
CLK
CE
1
Input-
Global write enable input, active LOW.
When asserted LOW on the rising edge of CLK, a global write
synchronous is conducted (all bytes are written, regardless of the values on BW
[A:D]
and BWE).
Input-
Byte write enable input, active LOW.
Sampled on the rising edge of CLK. This signal must be asserted
synchronous LOW to conduct a byte write.
Input-
clock
Clock input.
Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input-
Chip enable 1 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
2
synchronous and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is sampled only when a
new external address is loaded.
Input-
Chip enable 2 input, active HIGH.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
synchronous and CE
3
to select/deselect the device. CE
2
is sampled only when a new external address is loaded.
Input-
Chip enable 3 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
synchronous and CE
2
to select/deselect the device. CE
3
is sampled only when a new external address is loaded.
Input-
Output enable, asynchronous input, active LOW.
Controls the direction of the I/O pins. When LOW,
asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
Input-
Advance input signal, sampled on the rising edge of CLK, active LOW.
When asserted, it
synchronous automatically increments the address in a burst cycle.
Input-
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE
1
is deasserted HIGH.
Input-
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Input-
ZZ “sleep” input, active HIGH.
When asserted HIGH places the device in a non-time-critical “sleep”
asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull-down.
CE
2
CE
3
OE
ADV
ADSP
ADSC
ZZ
[2]
Note
2. Errata:
The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see
"Errata"
on page 20.
Document Number: 38-05520 Rev. *R
Page 4 of 23
CY7C1339G
Pin Definitions
(continued)
Name
DQs
I/O
Description
I/O-
Bidirectional data I/O lines.
As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed
in a tri-state condition.
Power supply
Power supply inputs to the core of the device.
Ground
I/O power
supply
I/O ground
Input-
static
–
Ground for the core of the device.
Power supply for the I/O circuitry.
Ground for the I/O circuitry.
Selects burst order.
When tied to GND selects linear burst sequence. When tied to V
DD
or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode pin has an internal pull-up.
No Connects.
Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M, NC/288M,
NC/576M and NC/1G are address expansion pins are not internally connected to the die.
V
DD
V
SS
V
DDQ
V
SSQ
MODE
NC,
NC/9M,
NC/18M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
Document Number: 38-05520 Rev. *R
Page 5 of 23
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
